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21. 发明授权

US07747820B2 Managing working set use of a cache via page coloring 有权
标题翻译：通过页面着色来管理缓存的工作集
公开(公告)号：US07747820B2
公开(公告)日：2010-06-29
申请号：US11818727
申请日：2007-06-15
申请人： Bradford Beckmann , Bradley M. Waters
发明人： Bradford Beckmann , Bradley M. Waters
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/1054 , G06F12/0842 , G06F2212/653
摘要： A processor cache is indexed by a group of distinct page colors. The use of this cache by different working sets is controlled using page coloring. Translations of virtual addresses of the instructions and/or data of a working set are constrained to physical addresses the page colors of which are in a subgroup of the group of distinct page colors.
摘要翻译：处理器缓存由一组不同的页面颜色索引。使用页面着色来控制不同工作集使用此缓存。指令和/或工作集的数据的虚拟地址的翻译被限制为其页面颜色位于不同页面颜色组的子组中的物理地址。

22. 发明授权

US6016529A Memory allocation technique for maintaining an even distribution of cache page addresses within a data structure 失效
标题翻译：用于维持数据结构中高速缓存页地址均匀分布的内存分配技术
公开(公告)号：US6016529A
公开(公告)日：2000-01-18
申请号：US978940
申请日：1997-11-26
申请人： Larry William Woodman
发明人： Larry William Woodman
IPC分类号： G06F12/08 , G06F12/10 , G06F12/12 , G06F17/30
CPC分类号： G06F12/10 , G06F12/0864 , G06F12/121 , G06F2212/653 , Y10S707/99953
摘要： In a computer system, a data structure is provided in memory for storing one or more data files from an external device. The data files stored in the data structure are accessible by a number of processes executing in the computer system. The computer system includes a storage device such as a cache for storing data from a subset of pages of the memory. Each of the pages of the cache is referred to as a cache page, having an associated cache page address. A physical address is allocated for storing each page of a retrieved data file stored in the data structure such that a cache page address portion of the physical address is selected from the available cache page addresses. The physical address is further selected such that the cache page addresses are substantially evenly distributed amongst the pages of the retrieved data file and the data structure in order to minimize thrashing in the cache and enhance performance.
摘要翻译：在计算机系统中，在存储器中提供数据结构，用于存储来自外部设备的一个或多个数据文件。存储在数据结构中的数据文件可通过在计算机系统中执行的多个进程来访问。计算机系统包括诸如用于从存储器的页面的子集存储数据的高速缓存的存储设备。高速缓存的每个页面被称为具有关联的高速缓存页地址的高速缓存页。分配物理地址用于存储存储在数据结构中的检索数据文件的每一页，使得从可用的高速缓存页地址中选择物理地址的高速缓存页地址部分。进一步选择物理地址，使得高速缓存页地址基本均匀地分布在检索的数据文件和数据结构的页面中，以便最小化缓存中的抖动并增强性能。

23. 发明授权

US5442571A Method and apparatus for cache miss reduction by simulating cache associativity 失效
标题翻译：通过模拟缓存关联性来缓存未命中减少的方法和装置
公开(公告)号：US5442571A
公开(公告)日：1995-08-15
申请号：US250315
申请日：1994-05-27
申请人： Richard L. Sites
发明人： Richard L. Sites
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/0864 , G06F12/1054 , G06F2212/653
摘要： A computer system using virtual memory addressing and having a direct-mapped cache is operated in a manner to simulate the effect of a set associative cache by detecting cache misses and remapping pages in the main memory so that memory references which would have caused thrashing can instead coexist in the cache. Two memory addresses which are in different pages but which map to the same location in the cache may not reside in the direct-mapped cache at the same time, so alternate reference to these addresses by a task executing on the CPU would cause thrashing. However, if the location of one of these addresses in main memory is changed, the data items having these addresses can coexist in the cache, and performance will be markedly improved because thrashing will no longer result. For a CPU executing a virtual memory operating system, a page of data or instructions can be moved to a different physical page frame but remain the same virtual address. This is accomplished by simply updating the page-mapping tables to reflect the new physical location of the page, and copying the data from the old page frame to the new one. The thrashing condition is detected and corrected dynamically by latching cache miss addresses and periodically sampling the latch, then remapping pages containing the addresses found upon sampling. The direct-mapped cache must be large enough to hold two or more pages.
摘要翻译：使用虚拟存储器寻址并具有直接映射高速缓存的计算机系统以通过检测主存储器中的高速缓存未命中和重新映射页面来模拟集合关联高速缓存的效果的方式操作，使得可能导致thrashing的存储器引用可以改为在缓存中并存。位于不同页面但映射到高速缓存中相同位置的两个内存地址可能不会同时驻留在直接映射高速缓存中，因此在CPU上执行的任务对这些地址的备用引用将导致颠覆。然而，如果主存储器中的这些地址之一的位置改变，则具有这些地址的数据项可以在高速缓存中共存，并且性能将被显着改善，因为不再产生抖动。对于执行虚拟存储器操作系统的CPU，可以将一页数据或指令移动到不同的物理页框，但保持相同的虚拟地址。这是通过简单地更新页面映射表来反映页面的新的物理位置，并将数据从旧页面框架复制到新的页面框架来实现的。通过锁存缓存未命中地址并周期性地对锁存器进行采样来检测和纠正抖动条件，然后重新映射包含在采样时找到的地址的页面。直接映射缓存必须足够大以容纳两个或多个页面。

24. 发明授权

US09672148B1 Methods and apparatus for direct cache-line access to attached storage with cache 有权
公开(公告)号：US09672148B1
公开(公告)日：2017-06-06
申请号：US14318939
申请日：2014-06-30
申请人： EMC Corporation
发明人： Adrian Michaud , Roy E. Clark
IPC分类号： G06F12/02 , G06F12/08 , G06F12/0802 , G06F12/1009
CPC分类号： G06F12/0868 , G06F3/0685 , G06F9/50 , G06F12/0246 , G06F12/08 , G06F12/0802 , G06F12/0811 , G06F12/0835 , G06F12/0873 , G06F12/1009 , G06F12/126 , G06F17/30 , G06F2212/1044 , G06F2212/1048 , G06F2212/222 , G06F2212/6046 , G06F2212/621 , G06F2212/653 , G06F2212/657 , G06F2212/7201 , G11C7/1072 , G11C11/40607
摘要： Methods and apparatus to provide application access to a flash device having page cache memory and storage class memory via a bus by mapping a user process virtual address space, wherein the process for the application resides on a host having a processor with direct cache-line access to the page cache memory, wherein the user process virtual address space includes at least a partial mapping of physical address windows for one or more separate flash devices.

25. 发明申请

US20160077946A1 PAGE RESOLUTION STATUS REPORTING 有权
标题翻译：页面分辨率状态报告
公开(公告)号：US20160077946A1
公开(公告)日：2016-03-17
申请号：US14846870
申请日：2015-09-07
申请人： Mellanox Technologies Ltd.
发明人： Shlomo Raikin , Shachar Raindel , Noam Bloch , Liran Liss
IPC分类号： G06F11/30 , G06F13/38 , G06F12/08 , G06F13/16 , G11C7/10 , G06F12/10
CPC分类号： G06F11/3065 , G06F12/0891 , G06F12/1009 , G06F12/109 , G06F13/1663 , G06F13/385 , G06F2212/653 , G06F2212/657
摘要： A method for data transfer includes receiving in a data transfer operation data to be written by a peripheral device to a specified virtual address in a random access memory (RAM) of a host computer. Upon receiving the data, it is detected that a page that contains the specified virtual address is marked as not present in a page table of the host computer. The peripheral device receives a notification that the page is not present and an estimate of a length of time that will be required to make the page available and selects a mode for handling of the data transfer operation depending upon the estimate.
摘要翻译：一种用于数据传送的方法包括：在主机计算机的随机存取存储器（RAM）中，在数据传送操作中接收要由外围设备写入的指定虚拟地址的数据。在接收到数据时，检测到包含指定的虚拟地址的页面被标记为不存在于主计算机的页表中。外围设备接收到页面不存在的通知以及使页面可用所需的时间长度的估计，并且根据估计选择用于处理数据传送操作的模式。

26. 发明授权

US09158710B2 Page coloring with color inheritance for memory pages 有权
标题翻译：页面着色与内存页面的颜色继承
公开(公告)号：US09158710B2
公开(公告)日：2015-10-13
申请号：US11513984
申请日：2006-08-31
申请人： Uday Savagaonkar
发明人： Uday Savagaonkar
IPC分类号： G06F12/14 , G06F12/10
CPC分类号： G06F12/1458 , G06F12/1009 , G06F12/145 , G06F2212/653
摘要： Apparatuses, methods, and media for page coloring with color inheritance for memory pages are disclosed. Some embodiments may include an interface to access a memory and a paging unit including translation logic, inheritance logic, and comparison logic. The translation logic translates a first address to a second address based on an entry in a data structure, wherein the first address is provided by an instruction stored in a first page in the memory and the entry includes a base address of a second page in the memory including the second address and a color of the second page. The inheritance logic may determine an effective current page color of the first page based on a color of the first page. The comparison logic may compare the effective current page color of the first page to the color of the second page. Other embodiments are disclosed and claimed.
摘要翻译：公开了用于内存页面的具有彩色继承的页面着色的装置，方法和媒体。一些实施例可以包括访问存储器的接口和包括翻译逻辑，继承逻辑和比较逻辑的寻呼单元。翻译逻辑基于数据结构中的条目将第一地址转换为第二地址，其中第一地址由存储在存储器中的第一页中的指令提供，并且条目包括第二地址的基地址存储器，其包括第二地址和第二页的颜色。继承逻辑可以基于第一页的颜色来确定第一页的有效的当前页面颜色。比较逻辑可以将第一页的有效当前页面颜色与第二页面的颜色进行比较。公开和要求保护其他实施例。

27. 发明授权

US08707006B2 Cache index coloring for virtual-address dynamic allocators 有权
标题翻译：虚拟地址动态分配器的缓存索引着色
公开(公告)号：US08707006B2
公开(公告)日：2014-04-22
申请号：US12899493
申请日：2010-10-06
申请人： David Dice
发明人： David Dice
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0223 , G06F12/023 , G06F12/0802 , G06F12/10 , G06F2212/653 , G06F2212/657
摘要： A method for managing a memory, including obtaining a number of indices and a cache line size of a cache memory, computing a cache page size by multiplying the number of indices by the cache line size, calculating a greatest common denominator (GCD) of the cache page size and a first size class, incrementing, in response to the GCD of the cache page size and the first size class exceeding the cache line size, the first size class to generate an updated first size class, calculating a GCD of the cache page size and the updated first size class, creating, in response to the GCD of the cache page size and the updated first size class being less than the cache line size, a first superblock in the memory including a first plurality of blocks of the updated first size class, and creating a second superblock in the memory.
摘要翻译：一种用于管理存储器的方法，包括获得多个索引和高速缓存存储器的高速缓存行大小，通过将索引数乘以高速缓存行大小来计算高速缓存页大小，计算最大公分母（GCD）缓存页面大小和第一大小类别，响应于高速缓存页大小的GCD和超过高速缓存行大小的第一大小类而递增，生成更新的第一大小类的第一大小类，计算高速缓存的GCD 页面大小和更新的第一大小类别，响应于缓存页面大小的GCD和更新的第一大小类别小于高速缓存行大小，创建存储器中的第一超级块，其包括更新的第一大小块第一大小类，并在内存中创建第二个超级块。

28. 发明授权

US06469705B1 Cache addressing 有权
标题翻译：缓存寻址
公开(公告)号：US06469705B1
公开(公告)日：2002-10-22
申请号：US09400557
申请日：1999-09-21
申请人： Benoit Belley
发明人： Benoit Belley
IPC分类号： G09G539
CPC分类号： G06F12/1045 , G06F12/0897 , G06F2212/653
摘要： In a computer system, main memory is accessed via a cache. Locations in a main memory are accessed by a process with reference to addresses. Each address comprises virtual bits and physical address bits. Selected bits of the physical address bits identify areas in the cache. Permutations of the selected bits are used to identify buffer alignments in main memory, in response to an identification of requirements for the process.
摘要翻译：在计算机系统中，通过高速缓存访问主存储器。通过参考地址的进程访问主内存中的位置。每个地址包括虚拟位和物理地址位。物理地址位的选定位标识缓存中的区域。所选位的排列用于识别主存储器中的缓冲器对齐，以响应对该过程的要求的识别。

29. 发明授权

US5630097A Enhanced cache operation with remapping of pages for optimizing data relocation from addresses causing cache misses 失效
标题翻译：增强的缓存操作，重新映射页面，以优化从导致高速缓存未命中的地址的数据重定位
公开(公告)号：US5630097A
公开(公告)日：1997-05-13
申请号：US178487
申请日：1994-01-07
申请人： David A. Orbits , Kenneth D. Abramson , H. Bruce Butts, Jr.
发明人： David A. Orbits , Kenneth D. Abramson , H. Bruce Butts, Jr.
IPC分类号： G06F12/08 , G06F12/10 , G06F12/02
CPC分类号： G06F12/10 , G06F12/0864 , G06F2212/653
摘要： A computer system executing virtual memory management and having a cache is operated in a manner to reduce cache misses by remapping pages of physical memory from which cache misses are detected. The method includes detecting cache misses, as by observing cache fill operations on the system bus, and then remapping the pages in the main memory which contain the addresses of the most frequent cache misses, so that memory references causing thrashing can then coexist in different pages of the cache. For a CPU executing a virtual memory operating system, a page of data or instructions can be moved to a different physical page frame but remain at the same virtual address, by simply updating the page-mapping tables to reflect the new physical location of the page, and copying the data from the old page frame to the new one. The primary feature of the invention is to add bus activity sampling logic to the CPU and enhance the operating system to allow the operating system to detect when cache thrashing is occurring and remap data pages to new physical memory locations to eliminate the cache thrashing situation.
摘要翻译：执行虚拟存储器管理并具有高速缓存的计算机系统以通过重新映射检测到高速缓存未命中的物理存储器的页面来减少高速缓存未命中的方式操作。该方法包括检测高速缓存未命中，如通过观察系统总线上的高速缓存填充操作，然后重新映射主存储器中包含最频繁高速缓存未命中的地址的页面，使得引起颠簸的存储器引用可以在不同的页面中共存的缓存。对于执行虚拟存储器操作系统的CPU，可以通过简单地更新页面映射表来反映页面的新的物理位置，将一页数据或指令移动到不同的物理页面帧，但保持在相同的虚拟地址，并将数据从旧页框复制到新页。本发明的主要特征是将总线活动采样逻辑添加到CPU并增强操作系统以允许操作系统检测何时发生高速缓存抖动，并将数据页重新映射到新的物理存储器位置以消除高速缓存抖动情况。

30. 发明授权

US5410663A Method and system for cache memory congruence class management in a data processing system 失效
标题翻译：数据处理系统中高速缓存存储器一致性类管理的方法和系统
公开(公告)号：US5410663A
公开(公告)日：1995-04-25
申请号：US962436
申请日：1992-10-15
申请人： Robert A. Blackburn , Keith N. Langston , Peter G. Sutton
发明人： Robert A. Blackburn , Keith N. Langston , Peter G. Sutton
IPC分类号： G06F12/10 , G06F12/03
CPC分类号： G06F12/1045 , G06F2212/653
摘要： A method and system for cache memory congruence class management in a data processing system. A selected address within a data processing system will typically have a single real address, but may have multiple virtual addresses within multiple virtual address spaces in a multi-tasking system, each virtual address space including a segment index, a page index and a byte index. A memory cache may be utilized to improve processor performance by hashing a portion of each virtual memory address to an address within a congruence class in the cache; however, when the cache contains a greater number of congruence classes than the number of different byte index addresses the virtual memory addresses of a single real memory address may hash to different congruence classes, reducing the ability of the processor to rapidly locate data within the cache. The method and system prevents this problem by first determining whether or not a virtual memory address exists within any virtual memory space in the system which corresponds to a selected address in real memory, in response to a request for a virtual memory address corresponding to that selected address. If such a virtual memory address already exists, a new virtual memory address is assigned such that the new virtual memory address will hash to the same congruence class as the existing virtual memory address, greatly enhancing the processor's efficiency at retrieving data within the cache. In the event no existing virtual memory address within the data processing system corresponds to the selected address a virtual memory address may be arbitrarily assigned.
摘要翻译：一种数据处理系统中缓存存储器一致性管理的方法和系统。数据处理系统内的选定地址通常具有单个实际地址，但在多任务系统中可能具有多个虚拟地址空间内的多个虚拟地址，每个虚拟地址空间包括段索引，页索引和字节索引。可以利用存储器缓存来通过将每个虚拟存储器地址的一部分散列到高速缓存中的同余类中的地址来提高处理器性能; 然而，当缓存包含比不同字节索引地址的数量更多的一致类时，单个实际存储器地址的虚拟存储器地址可以散列到不同的一致类，从而降低处理器快速定位高速缓存内的数据的能力。该方法和系统响应于对与所选择的虚拟存储器地址的对应的请求，首先确定虚拟存储器地址是否存在于系统中对应于实际存储器中的所选地址的任何虚拟存储器空间内，从而防止该问题地址。如果这样的虚拟存储器地址已经存在，则分配新的虚拟存储器地址，使得新的虚拟存储器地址将散列到与现有虚拟存储器地址相同的同余类，从而大大提高了处理器在高速缓存中检索数据时的效率。在数据处理系统内没有现有的虚拟存储器地址对应于所选择的地址的情况下，可以任意地分配虚拟存储器地址。

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