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21. 发明授权

US5345521A Architecture for optical switch 失效
标题翻译：光开关架构
公开(公告)号：US5345521A
公开(公告)日：1994-09-06
申请号：US90862
申请日：1993-07-12
申请人： T. Gus McDonald , R. Mark Boysel
发明人： T. Gus McDonald , R. Mark Boysel
IPC分类号： G02B6/26 , G02B6/35 , G02B26/08 , H04Q3/52
CPC分类号： G02B6/3564 , G02B26/0841 , G02B6/3512 , G02B6/3556 , G02B6/358 , G02B6/3582 , G02B6/3584
摘要： An optical switching device with switch elements (224) similar to digital micromirror devices (DMD). The switching element (224) resides in a trench (216) between two elevated areas on the substrate (214a, 214b). Sending and receiving fibers (218a, 218b) face each other across the trench (216) with the switch element (224) between them. When the switch is ON, light travels through lenses (220a, 220b) in the trench (216) from one fiber (218b) to the other (218a). When the switch is flipped OFF, the element (224) is activated and blocks the light from the sending fiber (218b) by reflecting or absorbing the light from the sending fiber (218b). The switch is activated and possibly deactivated by addressing electrodes (226a, 226b) under the element (224), which deflects through an air gap towards the activated electrode (226b). For better deflection angles the posts can be arranged closer to one end of the element than the other. An alternate hinge architecture is also provided.
摘要翻译：具有类似于数字微镜器件（DMD）的开关元件（224）的光学开关器件。开关元件（224）位于衬底（214a，214b）上的两个升高区域之间的沟槽（216）中。发送和接收光纤（218a，218b）跨越沟槽（216）并与它们之间的开关元件（224）彼此面对。当开关接通时，光从沟槽216中的一个光纤218b到另一个218a通过透镜220a，220b。当开关翻转为OFF时，元件（224）被激活，并通过反射或吸收来自发送光纤（218b）的光来阻挡来自发送光纤（218b）的光。开关被激活并且可能通过寻址元件（224）下的电极（226a，226b）而被激活，该电极通过空气间隙朝向激活的电极（226b）偏转。为了获得更好的偏转角度，柱可以比另一个更靠近元件的一端。还提供了另一种铰链架构。

22. 发明授权

US5108941A Method of making metal-to-polysilicon capacitor 失效
标题翻译：制造金属到多晶硅电容器的方法
公开(公告)号：US5108941A
公开(公告)日：1992-04-28
申请号：US495870
申请日：1990-03-19
申请人： James L. Paterson , Howard L. Tigelaar
发明人： James L. Paterson , Howard L. Tigelaar
IPC分类号： H01L21/765 , H01L27/105 , H01L29/788 , H01L29/92
CPC分类号： H01L28/40 , H01L21/765 , H01L27/105 , H01L29/7881
摘要： A metal-to-polysilicon capacitor, a floating-gate transistor containing such a capacitor, and a method for making the same is disclosed. The bottom plate of the capacitor is formed over a field oxide structure, and the multilevel dielectric is deposited thereover. The multilevel dielectric is removed from the capacitor area, and an oxide/nitride dielectric is deposited over the exposed bottom plate and over the multilevel by way of LPCVD. A first layer of titanium/tungsten is preferably deposited prior to contact etch, and the contacts to moat and unrelated polysilicon are formed. Metallization is sputtered overall, and the metal and titanium/tungsten are cleared to leave the metallization filling the contact holes, and a capacitor having a titanium/tungsten and metal top plate.
摘要翻译：公开了一种金属到多晶硅电容器，含有这种电容器的浮栅晶体管及其制造方法。电容器的底板形成在场氧化物结构上，并且多层电介质沉积在其上。从电容器区域去除多层电介质，并通过LPCVD将氧化物/氮化物电介质沉积在暴露的底板上并在多层上沉积。优选在接触蚀刻之前沉积第一层钛/钨，并且形成与护套和不相关的多晶硅的接触。金属化整体溅射，金属和钛/钨被清除以留下填充接触孔的金属化，以及具有钛/钨和金属顶板的电容器。

23. 发明授权

US5094973A Trench pillar for wafer processing 失效
标题翻译：沟槽支柱用于晶圆加工
公开(公告)号：US5094973A
公开(公告)日：1992-03-10
申请号：US541676
申请日：1990-06-21
申请人： Harry F. Pang
发明人： Harry F. Pang
IPC分类号： H01L21/762 , H01L21/763
CPC分类号： H01L21/76224 , H01L21/763
摘要： A T-shaped trench intersection shaped to make uniform the wall-to-wall spacing at the trench intersection and prevent the formation of voids when the trench is filled with a conformal insulating material.
摘要翻译：一个T形沟槽交叉点，其形状使得沟槽交叉点处的壁到壁间距均匀，并且当沟槽填充有保形绝缘材料时，防止形成空隙。

24. 发明授权

US10608532B1 Power converter with multi-mode timing control 有权
公开(公告)号：US10608532B1
公开(公告)日：2020-03-31
申请号：US16425353
申请日：2019-05-29
申请人： Texas Instruments Incorporated
发明人： Guofeng Jin , Yueming Sun
IPC分类号： H02M3/156 , H02M1/14 , H02M1/08 , H02M1/00
摘要： A converter circuit includes a power stage circuit configured to convert an input voltage to an output voltage provided at an output, and a control circuit configured to control the power stage circuit. The control circuit is configured to operate in one of a pulse frequency modulation (“PFM”) mode and a pulse width modulation (“PWM”) mode depending on a current supplied to the output. The control circuit includes a multi-mode timer circuit configured to provide a switching signal to set an off time for each switching cycle of the power stage circuit during the PFM mode and during the PWM mode.

25. 发明申请

US20150295556A1 TEMPERATURE COMPENSATED BULK ACOUSTIC WAVE RESONATOR WITH A HIGH COUPLING COEFFICIENT 有权
标题翻译：具有高耦合系数的温度补偿式音量波形谐振器
公开(公告)号：US20150295556A1
公开(公告)日：2015-10-15
申请号：US14251637
申请日：2014-04-13
申请人： Texas Instrument Incorporated
发明人： Stuart M. Jacobsen , Rick L. Wise , Maria Wang , Ricky Alan Jackson , Nicholas S. Dellas , Django Earl Trombley
IPC分类号： H03H9/05 , H03H3/02 , H03H9/02
CPC分类号： H03H9/02102 , H03H9/175
摘要： The dominant frequency of a solidly mounted resonator (100/280/300/400) is substantially increased by reducing the thickness of each layer of each Bragg acoustic reflector (112/160/224/274) to have a thickness than is substantially equal to one-quarter of the wavelength of a frequency that is a higher harmonic resonant frequency of the fundamental resonant frequency of the solidly mounted resonator (100/280/300/400).
摘要翻译：固体安装的谐振器（100/280/300/400）的主频通过将每个布拉格反射镜（112/160/224/274）的每个层的厚度减小到基本上等于是固体谐振器的基本谐振频率的高次谐波频率的频率的四分之一（100/280/300/400）。

26. 发明授权

US08897088B2 Nonvolatile logic array with built-in test result signal 有权
标题翻译：具有内置测试结果信号的非易失性逻辑阵列
公开(公告)号：US08897088B2
公开(公告)日：2014-11-25
申请号：US13753771
申请日：2013-01-30
申请人： Texas Instruments Incorporated
发明人： Steven Craig Bartling , Sudhanshu Khanna
IPC分类号： G11C29/50 , G11C29/08 , G11C29/34 , G11C11/401 , G11C29/02
CPC分类号： G11C29/08 , G11C11/22 , G11C11/401 , G11C14/0072 , G11C29/02 , G11C29/12 , G11C29/34 , G11C29/50 , G11C29/50016 , G11C2029/0401
摘要： A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines. An AND gate is coupled to the m bit lines and has an output line coupled to an input of a test controller on the SoC. An OR gate is coupled to the m bit lines and has an output line coupled to an input of the test controller.
摘要翻译：片上系统（SoC）提供非易失性存储器阵列，其配置为n行x位的位单元。每个位单元被配置为存储一位数据。存在m个位线，每个位线耦合到位单元的m列的相应一个。存在m个写入驱动器，每个写入驱动器耦合到m个位线中的相应一个位线。与门耦合到m位线，并且具有耦合到SoC上的测试控制器的输入的输出线。 OR门耦合到m位线，并且具有耦合到测试控制器的输入的输出线。

27. 发明授权

US08320165B1 SRAM strap row substrate contact 有权
标题翻译： SRAM带行底板接触
公开(公告)号：US08320165B1
公开(公告)日：2012-11-27
申请号：US13301217
申请日：2011-11-21
申请人： Robert R. Garcia , Theodore W. Houston
发明人： Robert R. Garcia , Theodore W. Houston
IPC分类号： G11C11/00
CPC分类号： H01L27/1116 , H01L21/76895 , H01L27/0207 , H01L27/1104
摘要： An integrated circuit containing an SRAM array having a strap row. The strap row has a substrate contact structure that includes a substrate contact plug and a tap layer.
摘要翻译：包含具有带排的SRAM阵列的集成电路。带排具有包括衬底接触插塞和抽头层的衬底接触结构。

28. 发明申请

US20100072600A1 FINE-PITCH OBLONG SOLDER CONNECTIONS FOR STACKING MULTI-CHIP PACKAGES 审中-公开
标题翻译：用于堆叠多芯片包的精细钻头连接焊接连接
公开(公告)号：US20100072600A1
公开(公告)日：2010-03-25
申请号：US12487346
申请日：2009-06-18
申请人： Mark A. GERBER
发明人： Mark A. GERBER
IPC分类号： H01L25/065 , H01L23/48 , H01L21/50 , H01L21/78
CPC分类号： H01L24/97 , H01L21/561 , H01L23/3128 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/04042 , H01L2224/16225 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2224/97 , H01L2225/06558 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/1433 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H01L2224/85 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor PoP device (100) includes a first device (101) with a first substrate (110) having on its first side (110a) a stack (115) of at least two chips, first contact pads (111), and a first package (116) having a height (116a) and a top surface (116b). Via holes (130) extend from the top package surface through the package height to the first contact pads; the vias have straight sidewalls and a diameter at the top surface of less than 75% of the height. The PoP further includes a second packaged device (102) with a second substrate (120) facing the top surface (116b) of the first package; substrate (120) has contact pads (121) in line with the first pads (111). Solder bodies (103) fill the vias (130) and connect the pads (121) with the respective first pads (111). In the fabrication method of first device (101), the vias (130) are opened through the complete package thickness (116a); thereafter, enough solder balls are filled into each via to insure contact with the respective solder body attached to the second package.
摘要翻译：半导体PoP器件（100）包括具有第一衬底（110）的第一器件（101），第一衬底（110）在其第一侧（110a）上具有至少两个芯片的堆叠（115），第一接触焊盘（111）具有高度（116a）和顶表面（116b）的包装（116）。通孔（130）从顶部封装表面延伸穿过封装高度到第一接触焊盘; 通孔具有直的侧壁，顶表面的直径小于高度的75％。 PoP还包括具有面向第一封装的顶表面（116b）的第二衬底（120）的第二封装器件（102）衬底（120）具有与第一焊盘（111）成一直线的接触焊盘（121）。焊体（103）填充通孔（130）并将焊盘（121）与相应的第一焊盘（111）连接。在第一装置（101）的制造方法中，通孔（130）通过整个封装厚度（116a）打开; 此后，足够的焊球被填充到每个通孔中以确保与附接到第二封装的相应焊接体接触。

29. 发明授权

US07630135B2 Two-dimensional blazed MEMS granting 有权
标题翻译：二维闪耀的MEMS授权
公开(公告)号：US07630135B2
公开(公告)日：2009-12-08
申请号：US11224336
申请日：2005-09-12
申请人： Benjamin L. Lee , Claude E. Tew , Walter M. Duncan
发明人： Benjamin L. Lee , Claude E. Tew , Walter M. Duncan
IPC分类号： G02B5/18 , H04J14/02
CPC分类号： G02B5/1828 , G02B26/0841
摘要： A method for assuring a blazed condition in a DMD device used in telecommunications applications. By meeting certain conditions in the fabrication and operation of the DMD, the device can achieve a blazed condition and be very effective in switching near monochromatic spatially coherent light, thereby opening up a whole new application field for such devices. This method determines the optimal pixel pitch and mirror tilt angle for a given incident angle and wavelength of near monochromatic spatially coherent light to assure blazed operating conditions. The Fraunhofer envelope is determined by convolving the Fourier transforms of the mirror aperture and the delta function at the center of each mirror and then aligning the center of this envelope with a diffraction order to provide a blazed condition. The method of the present invention presents a formula for precisely determining the mirror pitch and tilt angle to assure that a blazed condition exists for a given incident angle and wavelength of near monochromatic spatially coherent light. Considerations for the special case, know as Littrow conditions, where the incident and the reflected light transverse the same path, are also given. This case is particularly attractive for fiber optic/telecommunication applications since the same optics can be used for incoming and outgoing (reflected) light.
摘要翻译：一种用于确保在电信应用中使用的DMD设备中的闪耀状态的方法。通过满足DMD的制造和操作的某些条件，该装置可以实现闪耀状态，并且在切换近似单色空间相干光时非常有效，从而为这种装置开辟了全新的应用领域。该方法确定给定入射角和接近单色空间相干光的波长的最佳像素间距和镜面倾斜角，以确保闪耀的操作条件。 Fraunhofer包络是通过将镜面孔径的傅里叶变换和Δ函数卷积在每个反射镜的中心，然后将该信封的中心与衍射级对齐以提供闪耀状态来确定的。本发明的方法提出了用于精确地确定镜间距和倾斜角的公式，以确保对于给定的入射角和接近单色空间相干光的波长存在闪耀状态。特殊情况的注意事项，也被称为Littrow条件，事件和反射光横向相同的路径。这种情况对于光纤/电信应用是特别有吸引力的，因为相同的光学器件可以用于输入和输出（反射）的光。

30. 发明授权

US07095121B2 Metallic strain-absorbing layer for improved fatigue resistance of solder-attached devices 有权
标题翻译：金属应变吸收层，用于改善焊接装置的抗疲劳性能
公开(公告)号：US07095121B2
公开(公告)日：2006-08-22
申请号：US10205455
申请日：2002-07-25
申请人： John P. Tellkamp
发明人： John P. Tellkamp
IPC分类号： H01L23/48
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05572 , H01L2224/13099 , H01L2224/13109 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： An integrated circuit chip 501 has a plurality of contact pads (FIG. 5B) to be connected by reflow attachment 510 to outside parts. The chip comprises a deposited layer 505 of nickel/titanium alloy on each of the pads; the alloy has a composition and crystalline structure operable in reversible phase transitions under thermomechanical stress, whereby mechanical strain is absorbed by the alloy layer. Preferably, the alloy has between 55.0 and 56.0 weight % nickel, between 44.0 and 45.0 weight % titanium, and a thickness in the range from 0.3 to 6.0 μm, recrystallized after deposition in a temperature range from 450 to 600° C. for a time period between 4 and 6 min. A layer 506 of solderable metal is on the alloy, operable as diffusion barrier after reflow attachment.
摘要翻译：集成电路芯片501具有通过回流附件510连接到外部部分的多个接触焊盘（图5B）。该芯片包括每个焊盘上的镍/钛合金沉积层505; 该合金具有在热机械应力下在可逆相变中可操作的组成和晶体结构，由此机械应变被合金层吸收。优选地，该合金的镍含量为55.0-56.0重量％，钛为44.0-45.0重量％，厚度为0.3-6.0μm，在450-600℃的温度范围内沉积后重结晶一段时间时间为4至6分钟。可焊接金属的层506在合金上，在回流附着之后可用作扩散阻挡层。

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