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21. 发明申请

US20210216321A1 Control of Data Transfer Between Processors 有权
公开(公告)号：US20210216321A1
公开(公告)日：2021-07-15
申请号：US16844314
申请日：2020-04-09
申请人： Graphcore Limited
发明人： Lars Paul HUSE
IPC分类号： G06F9/30 , G06F15/80
摘要： A data processing system comprising a plurality of processors, wherein each of the processors is configured to perform data transfer operations to transfer outgoing data to one or more others of the processors during a first of the exchange stages; receive incoming data from the one or more others of the processors during the first of the exchange stages; determine further outgoing data in dependence upon at least part of the incoming data; count an amount of at least part the incoming data received during the first of the exchange stages from the one or more others of the processors; and in response to determining that the amount of the at least part of the incoming data received has reached a predefined amount, perform data transfer operations to transfer the further outgoing data to the one or more others of the processors during a second of the exchange stages.

22. 发明申请

US20210200602A1 Sync Groupings 有权
公开(公告)号：US20210200602A1
公开(公告)日：2021-07-01
申请号：US17125249
申请日：2020-12-17
申请人： Graphcore Limited
发明人： Brian MANULA , Daniel John Pelham WILKINSON
IPC分类号： G06F9/52 , G06F13/20
摘要： A gateway implementing multiple independent sync networks. The independent sync networks can be used to allow for synchronisation between different synchronisation groups of accelerators. The independent sync networks allow synchronisations to be carried out asynchronously and simultaneously. The gateway has sync propagation circuitry that receives a first synchronisation request for an upcoming exchange phase and propagates this sync request through a first sync network. The first synchronisation request is a request for synchronisation between subsystems of a first synchronisation group. The sync propagation circuitry of the gateway also receives a second synchronisation request for a different exchange phase and propagates this sync request through the second sync network. The second synchronisation request is a request for synchronisation between subsystems of a second synchronisation group. The two exchange phases overlap in time. Therefore, the syncs are simultaneous and asynchronous.

23. 发明申请

US20210191731A1 Communication in a Computer Having Multiple Processors 有权
公开(公告)号：US20210191731A1
公开(公告)日：2021-06-24
申请号：US16840988
申请日：2020-04-06
申请人： Graphcore Limited
发明人： Richard OSBORNE , Matthew FYLES
IPC分类号： G06F9/38 , G06F9/48 , G06F9/52 , G06F9/30 , G06F15/80 , G06N20/00 , G06N3/08
摘要： A computer comprising a plurality of processors, each of which are configured to perform operations on data during a compute phase for the computer and, following a pre-compiled synchronisation barrier, exchange data with at least one other of the processors during an exchange phase for the computer, wherein of the processors in the computer is indexed and the data exchange operations carried out by each processor in the exchange phase depend upon its index value.

24. 发明申请

US20210191488A1 Reactive Droop Limiter 有权
公开(公告)号：US20210191488A1
公开(公告)日：2021-06-24
申请号：US16842859
申请日：2020-04-08
申请人： Graphcore Limited
发明人： Stephen FELIX , Daniel WILKINSON
IPC分类号： G06F1/30 , G06F1/3206 , G06F1/08
摘要： During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly addressing this droop so as to reduce the probability of circuit timing failures. This problem is addressed by provided an apparatus that is configured to detect the droop and react to mitigate the droop. The apparatus includes a frequency divider that is configured to receive an output of a clock signal generator (e.g. a phase locked loop) and produce an output signal in which a predefined fraction of the clock pulses in the output of the clock signal generator are removed from the output signal. By reducing the frequency of the clock signal in this way (as may be understood by examining equation 3) VDD is increased, hence mitigating the voltage droop. This technique provides a fast throttling mechanism that prevents excessive VDD droop across the processor.

25. 发明授权

US11023290B2 Synchronization amongst processor tiles 有权
公开(公告)号：US11023290B2
公开(公告)日：2021-06-01
申请号：US15885972
申请日：2018-02-01
申请人： Graphcore Limited
发明人： Daniel John Pelham Wilkinson , Simon Christian Knowles , Matthew David Fyles , Alan Graham Alexander , Stephen Felix
IPC分类号： G06F9/30 , G06F9/52 , G06F9/38 , G06F15/80 , G06N20/00 , G06F9/48
摘要： A processing system comprising an arrangement of tiles and an interconnect between the tiles. The interconnect comprises synchronization logic for coordinating a barrier synchronization to be performed between a group of the tiles. The instruction set comprises a synchronization instruction taking an operand which selects one of a plurality of available modes each specifying a different membership of the group. Execution of the synchronization instruction cause a synchronization request to be transmitted from the respective tile to the synchronization logic, and instruction issue to be suspended on the respective tile pending a synchronization acknowledgement being received back from the synchronization logic. In response to receiving the synchronization request from all the tiles in the group as specified by the operand of the synchronization instruction, the synchronization logic returns the synchronization acknowledgment to the tiles in the specified group.

26. 发明授权

US10963003B2 Synchronization in a multi-tile processing array 有权
公开(公告)号：US10963003B2
公开(公告)日：2021-03-30
申请号：US16165978
申请日：2018-10-19
申请人： Graphcore Limited
发明人： Simon Christian Knowles , Daniel John Pelham Wilkinson , Richard Luke Southwell Osborne , Alan Graham Alexander , Stephen Felix , Jonathan Mangnall , David Lacey
IPC分类号： G06F1/12 , G06F9/30 , G06N20/00 , G06N5/02 , G06N5/04
摘要： The invention relates to a computer comprising: a plurality of processing units each having instruction storage holding a local program, an execution unit executing the local program, data storage for holding data; an input interface with a set of input wires, and an output interface with a set of output wires; a switching fabric connected to each of the processing units by the respective set of output wires and connectable to each of the processing units by the respective input wires via switching circuitry controllable by each processing unit; a synchronisation module operable to generate a synchronisation signal to control the computer to switch between a compute phase and an exchange phase, wherein the processing units are configured to execute their local programs according to a common clock, the local programs being such that in the exchange phase at least one processing unit executes a send instruction from its local program to transmit at a transmit time a data packet onto its output set of connection wires, the data packet being destined for at least one recipient processing unit but having no destination identifier, and at a predetermined switch time the recipient processing unit executes a switch control instruction from its local program to control its switching circuitry to connect its input set of wires to the switching fabric to receive the data packet at a receive time, the transmit time and, switch time and receive time being governed by the common clock with respect to the synchronisation signal.

27. 发明授权

US10949266B2 Synchronization and exchange of data between processors 有权
公开(公告)号：US10949266B2
公开(公告)日：2021-03-16
申请号：US16538980
申请日：2019-08-13
申请人： Graphcore Limited
发明人： David Lacey , Daniel John Pelham Wilkinson , Richard Luke Southwell Osborne , Matthew David Fyles
IPC分类号： G06F16/901 , G06F9/30 , G06F15/167 , G06F15/173 , G06F9/48 , G06F9/52 , G06F9/38 , G06F9/54 , H04L12/801 , H04L29/06 , H04L29/08
摘要： A system comprising: a first subsystem comprising one or more first processors, and a second subsystem comprising one or more second processors. The second subsystem is configured to process code over a series of steps delineated by barrier synchronizations, and in a current step, to send a descriptor to the first subsystem specifying a value of each of one or more parameters of each of one or more interactions that the second subsystem is programmed to perform with the first subsystem via an inter-processor interconnect in a subsequent step. The first subsystem is configured to execute a portion of code to perform one or more preparatory operations, based on the specified values of at least one of the one or more parameters of each interaction as specified by the descriptor, to prepare for said one or more interactions prior to the barrier synchronization leading into the subsequent phase.

28. 发明授权

US10802536B2 Compiler method 有权
公开(公告)号：US10802536B2
公开(公告)日：2020-10-13
申请号：US15886053
申请日：2018-02-01
申请人： Graphcore Limited
发明人： Simon Christian Knowles , Daniel John Pelham Wilkinson , Richard Luke Southwell Osborne , Alan Graham Alexander , Stephen Felix , Jonathan Mangnall , David Lacey
IPC分类号： G06F1/12 , G06F9/52 , G06F9/30 , G06F9/54 , G06F9/38 , G06F15/173 , G06N20/00
摘要： The invention relates to a computer implemented method of generating multiple programs to deliver a computerised function, each program to be executed in a processing unit of a computer comprising a plurality of processing units each having instruction storage for holding a local program, an execution unit for executing the local program and data storage for holding data, a switching fabric connected to an output interface of each processing unit and connectable to an input interface of each processing unit by switching circuitry controllable by each processing unit, and a synchronisation module operable to generate a synchronisation signal, the method comprising: generating a local program for each processing unit comprising a sequence of executable instructions; determining for each processing unit a relative time of execution of instructions of each local program whereby a local program allocated to one processing unit is scheduled to execute with a predetermined delay relative to a synchronisation signal a send instruction to transmit at least one data packet at a predetermined transmit time, relative to the synchronisation signal, destined for a recipient processing unit but having no destination identifier, and a local program allocated to the recipient processing unit is scheduled to execute at a predetermined switch time a switch control instruction to control the switching circuitry to connect its processing unit wire to the switching fabric to receive the data packet at a receive time.

29. 发明申请

US20200233670A1 DOUBLE LOAD INSTRUCTION 审中-公开
公开(公告)号：US20200233670A1
公开(公告)日：2020-07-23
申请号：US16389682
申请日：2019-04-19
申请人： Graphcore Limited
发明人： Alan Graham Alexander , Simon Christian Knowles , Mrudula Chidambar Gore
IPC分类号： G06F9/345 , G06F9/30 , G06N3/04
摘要： A processor comprising an execution unit, memory and one or more register files. The execution unit is configured to execute instances of machine code instructions from an instruction set. The types of instruction defined in the instruction set include a double-load instruction for loading from the memory to at least one of the one or more register files. The execution unit is configured so as, when the load instruction is executed, to perform a first load operation strided by a fixed stride, and a second load operation strided by a variable stride, the variable stride being specified in a variable stride register in one of the one or more register files.

30. 发明授权

US10705998B1 Exchange of data between processor modules 有权
公开(公告)号：US10705998B1
公开(公告)日：2020-07-07
申请号：US16276926
申请日：2019-02-15
申请人： Graphcore Limited
发明人： Daniel John Pelham Wilkinson , Alan Graham Alexander
IPC分类号： G06F9/46 , G06F13/40 , G06F9/30 , G06F8/41
摘要： A processing system comprising: multiple processor modules, each comprising a respective execution unit memory; and an interconnect for exchanging data between different sets of the processor modules. A group of the processor modules operates in a series of BSP supersteps. For the exchange phase of each superstep, each receiving processor module that is to receive data from outside its own set is pre-programmed with a value representing the number of units of data to receive. Starting from the pre-programmed value, it then counts out the number of data units remaining to be received each time a data unit is received. Each receiving processor module is further arranged to perform an exchange synchronization whereby, before advancing from the exchange phase to the compute phase of the current superstep, the receiving processor module waits until no units of data remain to be received according to the count.

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