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21. 发明授权

US07087972B1 Magnetoelectronic devices utilizing protective capping layers and methods of fabricating the same 有权
标题翻译：使用保护盖层的磁电子器件及其制造方法
公开(公告)号：US07087972B1
公开(公告)日：2006-08-08
申请号：US11048015
申请日：2005-01-31
申请人： J. Jack Ren , Brian R. Butcher , Mark A. Durlam , Gregory W. Grynkewich
发明人： J. Jack Ren , Brian R. Butcher , Mark A. Durlam , Gregory W. Grynkewich
IPC分类号： H01L29/82
CPC分类号： H01L43/12 , H01L27/228
摘要： Magnetoelectronic device structures and methods for fabricating the same are provided. One method comprises forming a first and a second conductor. The first conductor is electrically coupled to an interconnect stack. A first insulating layer is deposited overlying the first conductor and the second conductor. A via is etched to substantially expose the first conductor. A protective capping layer is deposited by electroless deposition within the via and is electrically coupled to the first conductor. A magnetic memory element layer is formed within the via and overlying the second insulating layer and the second conductor.
摘要翻译：提供了磁电子器件结构及其制造方法。一种方法包括形成第一和第二导体。第一导体电耦合到互连叠层。沉积在第一导体和第二导体上的第一绝缘层。蚀刻通孔以基本上暴露第一导体。通过无孔沉积在通孔内沉积保护性覆盖层并电耦合到第一导体。磁通存储元件层形成在通孔内并覆盖第二绝缘层和第二导体。

22. 发明授权

US06936763B2 Magnetic shielding for electronic circuits which include magnetic materials 有权
标题翻译：包括磁性材料的电子电路的磁屏蔽
公开(公告)号：US06936763B2
公开(公告)日：2005-08-30
申请号：US10184536
申请日：2002-06-28
申请人： Nicholas D. Rizzo , Mark A. Durlam , Michael J. Roll , Kelly Kyler , Jaynal A. Molla
发明人： Nicholas D. Rizzo , Mark A. Durlam , Michael J. Roll , Kelly Kyler , Jaynal A. Molla
IPC分类号： H01L21/68 , H01L21/8246 , H01L23/552 , H01L27/105 , H01L27/22 , H05K9/00 , H01B11/00
CPC分类号： H05K9/0075 , H01L21/6835 , H01L23/552 , H01L24/48 , H01L24/49 , H01L27/222 , H01L2221/68331 , H01L2224/48091 , H01L2224/48247 , H01L2224/4911 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19107 , H01L2924/3025 , H01L2224/45099 , H01L2224/05599
摘要： Shielded electronic integrated circuit apparatus (5) includes a substrate (10), with an eletronic integrated circuit (15) formed thereon, and a dielectric region (12) positioned on the electronic integrated circuit. The dielectric region and the substrate are substantially surrounded by lower and upper magnetic material regions (26, 30), deposited using electrochemical deposition, and magnetic material layers on each side (32, 34). Each of the lower and upper magnetic material regions preferably include a glue layer (36, 40), a seed layer (28, 24), and an electrochemically deposited magnetic material layer (26, 30). Generally, the electrochemically deposited magnetic material layer can be conveniently deposited by electroplating.
摘要翻译：屏蔽电子集成电路装置（5）包括其上形成有电子集成电路（15）的基板（10）和位于电子集成电路上的电介质区域（12）。电介质区域和衬底基本上被使用电化学沉积沉积的下部和上部磁性材料区域（26,30）围绕，并且在每一侧（32,34）上都具有磁性材料层。下部和上部磁性材料区域中的每一个优选地包括胶层（36,40），种子层（28,24）和电化学沉积的磁性材料层（26,30）。通常，电化学沉积的磁性材料层可以方便地通过电镀沉积。

23. 发明授权

US06911156B2 Methods for fabricating MRAM device structures 有权
标题翻译：制造MRAM器件结构的方法
公开(公告)号：US06911156B2
公开(公告)日：2005-06-28
申请号：US10417537
申请日：2003-04-16
申请人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Kelly Kyler , Kenneth H. Smith , Clarence J. Tracy
发明人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Kelly Kyler , Kenneth H. Smith , Clarence J. Tracy
IPC分类号： G11B5/127 , G11C11/16 , H01L21/00 , H01L43/12 , H04R31/00 , H05K3/02
CPC分类号： G11C11/16 , H01L43/12 , Y10T29/49041 , Y10T29/49044 , Y10T29/49156 , Y10T29/49165
摘要： A method for fabricating a magnetic memory element structure comprises providing a dielectric layer having a conducting via. A first magnetic layer is formed overlying the dielectric layer and is in electrical communication with the conducting via. A non-magnetic layer and a second magnetic layer are formed overlying the first magnetic layer. A first conductive layer is deposited overlying the second magnetic layer and is patterned. A portion of the second magnetic layer is exposed and is transformed to form an inactive portion and an active portion. The active portion comprises a portion of a memory element and the inactive portion comprises an insulator. A sidewall spacer is formed about at least one sidewall of the first conductive layer and a masking tab is formed that overlies a portion of the memory element and extends to overlie at least a portion of the conducting via.
摘要翻译：一种用于制造磁存储元件结构的方法，包括提供具有导电通孔的电介质层。第一磁性层形成在电介质层上并与导电通孔电连通。在第一磁性层上形成非磁性层和第二磁性层。将第一导电层沉积在第二磁性层上并被图案化。第二磁性层的一部分被暴露并被变换以形成非活性部分和活性部分。有源部分包括存储元件的一部分，非活性部分包括绝缘体。围绕第一导电层的至少一个侧壁形成侧壁间隔物，并且形成覆盖存储元件的一部分并延伸以覆盖导电通孔的至少一部分的掩蔽突片。

24. 发明授权

US06812040B2 Method of fabricating a self-aligned via contact for a magnetic memory element 失效
标题翻译：制造用于磁存储元件的自对准通孔接点的方法
公开(公告)号：US06812040B2
公开(公告)日：2004-11-02
申请号：US10095816
申请日：2002-03-12
申请人： Kelly Kyler , Saied N. Tehrani , John J. D'urso , Gregory W. Grynkewich , Mark A. Durlam , Brian Butcher
发明人： Kelly Kyler , Saied N. Tehrani , John J. D'urso , Gregory W. Grynkewich , Mark A. Durlam , Brian Butcher
IPC分类号： H01L2100
CPC分类号： H01L43/12 , B82Y10/00
摘要： A method of fabricating a magnetoresistive random access memory device comprising the steps of providing a substrate, forming a conductive layer positioned on the substrate, forming a magnetoresistive random access memory device positioned on conductive layer, forming a metal cap on the magnetoresistive random access memory device, and electroless plating a bump metal layer on the metal cap. The bump metal layer acts as a self-aligned via for a bit line subsequently formed thereon.
摘要翻译：一种制造磁阻随机存取存储器件的方法，包括以下步骤：提供衬底，形成位于衬底上的导电层，形成位于导电层上的磁阻随机存取存储器件，在磁阻随机存取存储器件上形成金属帽并且在金属盖上化学镀覆凸块金属层。凸块金属层用作随后在其上形成的位线的自对准通孔。

25. 发明授权

US06784510B1 Magnetoresistive random access memory device structures 有权
标题翻译：磁阻随机存取存储器件结构
公开(公告)号：US06784510B1
公开(公告)日：2004-08-31
申请号：US10417851
申请日：2003-04-16
申请人： Gregory W. Grynkewich , Mark Deherrera , Mark A. Durlam , Clarence J. Tracy
发明人： Gregory W. Grynkewich , Mark Deherrera , Mark A. Durlam , Clarence J. Tracy
IPC分类号： H01L2900
CPC分类号： H01L27/228 , B82Y10/00
摘要： A method for fabricating an MRAM device structure includes providing a substrate on which is formed a first transistor and a second transistor. An operative memory element device is formed in electrical contact with the first transistor. At least a portion of a false memory element device is formed in electrical contact with the second transistor. A first dielectric layer is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via to the at least a portion of a false memory element device and a second via to the operative memory element device. An electrically conductive interconnect layer is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device to the operative memory element device.
摘要翻译：一种用于制造MRAM器件结构的方法包括提供其上形成有第一晶体管和第二晶体管的衬底。操作存储元件装置形成为与第一晶体管电接触。假存储元件器件的至少一部分形成为与第二晶体管电接触。第一介电层沉积在伪存储元件器件和操作存储元件器件的至少一部分上。蚀刻第一电介质层以同时形成第一通孔到伪存储元件器件的至少一部分，并将第二通孔形成到操作存储元件器件。沉积导电互连层，使得导电互连层从假存储元件器件的至少一部分延伸到可操作存储元件器件。

26. 发明授权

US06760266B2 Sense amplifier and method for performing a read operation in a MRAM 有权
公开(公告)号：US06760266B2
公开(公告)日：2004-07-06
申请号：US10185566
申请日：2002-06-28
申请人： Bradley J. Garni , Mark F. Deherrera , Mark A. Durlam , Bradley N. Engel , Thomas W. Andre , Joseph J. Nahas , Chitra K. Subramanian
发明人： Bradley J. Garni , Mark F. Deherrera , Mark A. Durlam , Bradley N. Engel , Thomas W. Andre , Joseph J. Nahas , Chitra K. Subramanian
IPC分类号： G11C702
CPC分类号： G11C11/16 , G11C7/062 , G11C27/02
摘要： A sense amplifier (1300, 1500) is provided for sensing the state of a toggling type magnetoresistive random access memory (MRAM) cell without using a reference. The sense amplifier (1300, 1500) employs a sample-and-hold circuit (1336, 1508) combined with a current-to-voltage converter (1301, 1501), gain circuit (1303), and cross-coupled latch (1305, 1503) to sense the state of a bit. The sense amplifier (1300, 1500), first senses and holds a first state of the cell. The cell is toggled to a second state. Then, the sense amplifier (1300, 1500) compares the first state to the second state to determine the first state of a toggling type memory cell.

27. 发明授权

US07747926B2 Methods and apparatus for a memory device with self-healing reference bits 有权
标题翻译：具有自修复参考位的存储器件的方法和装置
公开(公告)号：US07747926B2
公开(公告)日：2010-06-29
申请号：US11416850
申请日：2006-05-02
申请人： Loren J. Wise , Thomas W. Andre , Mark A. Durlam , Eric J. Salter
发明人： Loren J. Wise , Thomas W. Andre , Mark A. Durlam , Eric J. Salter
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G06F11/1008 , G11C11/16
摘要： A memory device, such an MRAM device, includes self-healing reference bits (104) associated with a set of array bits (102). The memory performs an error detection step (e.g., using an error-correction coding (ECC) algorithm, to detect the presence of a set of errors within the data bits. One of the reference bits (104) is toggled to a different state if an error count is greater than a predetermined threshold. If the set of errors remains unchanged when subsequently read, the reference bit (104) is toggled back to its original state.
摘要翻译：诸如MRAM设备的存储器件包括与一组阵列位（102）相关联的自修复参考位（104）。存储器执行错误检测步骤（例如，使用纠错编码（ECC）算法）来检测数据位内的一组错误的存在，其中一个参考位（104）被切换到不同的状态，如果错误计数大于预定阈值，如果随后读取的错误集合保持不变，则将参考位（104）切换回其初始状态。

28. 发明授权

US07279341B2 Method for fabricating a flux concentrating system for use in a magnetoelectronics device 失效
标题翻译：制造用于磁电装置的通量集中系统的方法
公开(公告)号：US07279341B2
公开(公告)日：2007-10-09
申请号：US11125955
申请日：2005-05-09
申请人： Thomas V. Meixner , Gregory W. Grynkewich , Jaynal A. Molla , J. Jack Ren , Richard G. Williams , Brian R. Butcher , Mark A. Durlam
发明人： Thomas V. Meixner , Gregory W. Grynkewich , Jaynal A. Molla , J. Jack Ren , Richard G. Williams , Brian R. Butcher , Mark A. Durlam
IPC分类号： H01L21/465
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/16 , H01L43/12
摘要： A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.
摘要翻译：提供了一种用于制造用于磁电装置的通量集中系统（62）的方法。该方法包括以下步骤：提供在衬底（12）中形成的位线（10），并形成覆盖位线（10）和衬底（12）的第一材料层（24）。进行蚀刻以在第一材料层（24）中形成沟槽（58），并且在沟槽（52）中沉积包层（56）。缓冲材料层（58）形成在覆层（56）上，缓冲材料层（58）的一部分和包覆层（56）的一部分被去除。

29. 发明授权

US07144744B2 Magnetoresistive random access memory device structures and methods for fabricating the same 有权
标题翻译：磁阻随机存取存储器件结构及其制造方法
公开(公告)号：US07144744B2
公开(公告)日：2006-12-05
申请号：US10977003
申请日：2004-10-27
申请人： Mitchell T. Lien , Mark A. Durlam , Thomas V. Meixner , Loren J. Wise
发明人： Mitchell T. Lien , Mark A. Durlam , Thomas V. Meixner , Loren J. Wise
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , H01L21/76834 , H01L21/76841 , H01L21/76843
摘要： Magnetoelectronic memory element structures and methods for making such structures using a barrier layer as a material removal stop layer are provided. The methods comprise forming a digit line disposed at least partially within a dielectric layer. The dielectric material layer overlies an interconnect stack. A void space is etched in the dielectric layer to expose the interconnect stack. A conductive-barrier layer having a first portion and a second portion is deposited. The first portion overlies the digit line and the second portion is disposed within the void space and in electrical communication with the interconnect stack. A memory element layer is formed overlying the first portion and an electrode layer is deposited overlying the memory element layer. The electrode layer and the memory element layer are then patterned and etched.
摘要翻译：提供了使用阻挡层作为材料去除停止层来制造这种结构的磁电存储元件结构和方法。所述方法包括形成至少部分地设置在电介质层内的数字线。电介质材料层覆盖互连叠层。在电介质层中蚀刻空隙以暴露互连叠层。沉积具有第一部分和第二部分的导电阻挡层。第一部分覆盖数字线，第二部分设置在空隙空间内并与互连叠层电连通。形成覆盖在第一部分上的存储元件层，并且沉积覆盖存储元件层的电极层。然后对电极层和存储元件层进行图案化和蚀刻。

30. 发明授权

US07105363B2 Cladded conductor for use in a magnetoelectronics device and method for fabricating the same 失效
标题翻译：用于磁电子器件的包层导体及其制造方法
公开(公告)号：US07105363B2
公开(公告)日：2006-09-12
申请号：US11082617
申请日：2005-03-16
申请人： Mark A. Durlam , Jeffrey H. Baker , Brian R. Butcher , Mark F. Deherrera , John J. D'Urso , Earl D. Fuchs , Gregory W. Grynkewich , Kelly W. Kyler , Jaynal A. Molla , J. Jack Ren , Nicholas D. Rizzo
发明人： Mark A. Durlam , Jeffrey H. Baker , Brian R. Butcher , Mark F. Deherrera , John J. D'Urso , Earl D. Fuchs , Gregory W. Grynkewich , Kelly W. Kyler , Jaynal A. Molla , J. Jack Ren , Nicholas D. Rizzo
IPC分类号： H01L21/00
CPC分类号： H01L27/222 , G11C11/15 , H01L28/10 , H01L43/12
摘要： A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).
摘要翻译：提供一种用于制造用于磁电装置的包层导体（42）的方法。该方法包括提供衬底（10）并形成覆盖衬底（10）的导电阻挡层（12）。形成在导电阻挡层（12）上方的电介质层（16），并且在电介质层（16）的一部分内形成导电线（20）。去除电介质层（16），并且形成覆盖导线（20）的集流器（30）。

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