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21. 发明申请

US20060252354A1 METHODS AND DEVICES FOR SUPPORTING SUBSTRATES USING FLUIDS 失效
标题翻译：用于支持使用流体的基板的方法和装置
公开(公告)号：US20060252354A1
公开(公告)日：2006-11-09
申请号：US11125605
申请日：2005-05-09
申请人： Leonel Arana , Terry Sterrett , Devendra Natekar
发明人： Leonel Arana , Terry Sterrett , Devendra Natekar
IPC分类号： B24B1/00
CPC分类号： B24B7/228 , B24B41/068 , Y10T29/49998
摘要： Electronic device support and processing methods are described. One embodiment includes a method of processing an electronic device including solder bumps extending therefrom. The method includes providing at least one fluid selected from the group consisting of electrorheological fluids and magnorheological fluids on a support structure. The solder bumps extending from the electronic device are positioned in the fluid. The fluid is activated by applying a field selected from the group consisting of an electric field and a magnetic field to the fluid. The activated fluid mechanically holds the electronic device in place. A surface of the electronic device is polished while the electronic device is held in place by the activated fluid. The fluid is deactivated by removing the applied field from the fluid, and the electronic device is separated from the deactivated fluid. Other embodiments are described and claimed.
摘要翻译：描述电子设备支持和处理方法。一个实施例包括处理包括从其延伸的焊锡凸块的电子器件的方法。该方法包括在支撑结构上提供至少一种选自电流变流体和流变流体的流体。从电子设备延伸的焊料凸块位于流体中。通过将从电场和磁场组成的组中选出的场施加到流体来激活流体。活化流体将电子设备机械地保持在适当位置。电子设备的表面被抛光，同时电子设备被活化的流体保持就位。通过从流体中除去所施加的场，使流体失活，并且电子装置与去活化流体分离。描述和要求保护其他实施例。

22. 发明授权

US07049208B2 Method of manufacturing of thin based substrate 有权
标题翻译：薄基基板的制造方法
公开(公告)号：US07049208B2
公开(公告)日：2006-05-23
申请号：US10963489
申请日：2004-10-11
申请人： Sriram Muthukumar , Devendra Natekar
发明人： Sriram Muthukumar , Devendra Natekar
IPC分类号： H01L21/46
CPC分类号： H01L23/49827 , H01L21/486 , H01L21/76898 , H01L23/49822 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/01322 , H01L2924/15311 , H01L2924/00 , H01L2224/05599
摘要： Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die.
摘要翻译：本发明的实施例提供一种具有模具和基板的装置，其具有与模具的热膨胀系数相似的热膨胀系数。衬底可以包括硅基层。可以在距离模具更远的基底层的侧面上形成堆积层。

23. 发明申请

US20060079079A1 METHOD OF MANUFACTURING OF THIN BASED SUBSTRATE 有权
标题翻译：制造薄基板的方法
公开(公告)号：US20060079079A1
公开(公告)日：2006-04-13
申请号：US10963489
申请日：2004-10-11
申请人： Sriram Muthukumar , Devendra Natekar
发明人： Sriram Muthukumar , Devendra Natekar
IPC分类号： H01L21/4763
CPC分类号： H01L23/49827 , H01L21/486 , H01L21/76898 , H01L23/49822 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/01322 , H01L2924/15311 , H01L2924/00 , H01L2224/05599
摘要： Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die.
摘要翻译：本发明的实施例提供一种具有模具和基板的装置，其具有与模具的热膨胀系数相似的热膨胀系数。衬底可以包括硅基层。可以在距离模具更远的基底层的侧面上形成堆积层。

24. 发明申请

US20060038303A1 Etched interposer for integrated circuit devices 有权
公开(公告)号：US20060038303A1
公开(公告)日：2006-02-23
申请号：US10924396
申请日：2004-08-23
申请人： Terry Sterrett , Devendra Natekar
发明人： Terry Sterrett , Devendra Natekar
IPC分类号： H01L23/48
CPC分类号： H05K3/4038 , H01L21/486 , H01L23/49827 , H01L24/48 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2924/00014 , H01L2924/14 , H05K3/06 , H05K2201/09881 , H05K2201/10378 , H05K2201/2018 , H05K2203/0369 , H05K2203/1476 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer. In one embodiment, the interposer 106 includes columnar interconnects which may be fabricated by etching a conductive member such as copper foil, for example. In one application, the pitch or center to center spacing of the columnar interconnects may be defined by masking techniques to provide an interconnect pitch suitable for a particular application. In yet another aspect, etching rates may be controlled to provide height to width aspect ratios of the columnar interconnects which are suitable for various applications.

25. 发明授权

US07528006B2 Integrated circuit die containing particle-filled through-silicon metal vias with reduced thermal expansion 有权
标题翻译：集成电路管芯包含具有减少的热膨胀的颗粒填充的通过硅的金属通孔
公开(公告)号：US07528006B2
公开(公告)日：2009-05-05
申请号：US11174125
申请日：2005-06-30
申请人： Leonel Arana , Michael Newman , Devendra Natekar
发明人： Leonel Arana , Michael Newman , Devendra Natekar
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L21/2885 , H01L23/481 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/11 , H01L2224/11424 , H01L2224/11462 , H01L2224/1147 , H01L2224/13009 , H01L2224/13216 , H01L2224/13224 , H01L2224/13239 , H01L2224/13244 , H01L2224/13247 , H01L2224/13284 , H01L2224/13384 , H01L2224/13386 , H01L2924/00014 , H01L2924/0002 , H01L2924/01322 , H01L2924/12033 , H01L2924/14 , H01L2924/0105 , H01L2224/05552 , H01L2924/00
摘要： A method, apparatus and system with an electrically conductive through hole via of a composite material with a matrix forming a continuous phase and embedded particles, with a different material property than the matrix, forming a dispersed phase, the resulting composite material having a different material property than the matrix.
摘要翻译：一种具有导电通孔通孔的方法，装置和系统，其具有形成连续相的基质的复合材料的导电通孔，并且具有与基质不同的材料性质的嵌入的颗粒，形成分散相，所得复合材料具有不同的材料属性比矩阵。

26. 发明授权

US07443030B2 Thin silicon based substrate 有权
标题翻译：薄硅基底材
公开(公告)号：US07443030B2
公开(公告)日：2008-10-28
申请号：US11388354
申请日：2006-03-23
申请人： Sriram Muthukumar , Devendra Natekar
发明人： Sriram Muthukumar , Devendra Natekar
IPC分类号： H01L29/00
CPC分类号： H01L23/49827 , H01L21/486 , H01L21/76898 , H01L23/49822 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/01322 , H01L2924/15311 , H01L2924/00 , H01L2224/05599
摘要： Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die.
摘要翻译：本发明的实施例提供一种具有模具和基板的装置，其具有与模具的热膨胀系数相似的热膨胀系数。衬底可以包括硅基层。可以在距离模具更远的基底层的侧面上形成堆积层。

27. 发明授权

US07413995B2 Etched interposer for integrated circuit devices 有权
标题翻译：用于集成电路器件的蚀刻插入器
公开(公告)号：US07413995B2
公开(公告)日：2008-08-19
申请号：US10924396
申请日：2004-08-23
申请人： Terry L. Sterrett , Devendra Natekar
发明人： Terry L. Sterrett , Devendra Natekar
IPC分类号： H01L21/44 , H01L21/48
CPC分类号： H05K3/4038 , H01L21/486 , H01L23/49827 , H01L24/48 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2924/00014 , H01L2924/14 , H05K3/06 , H05K2201/09881 , H05K2201/10378 , H05K2201/2018 , H05K2203/0369 , H05K2203/1476 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer. In one embodiment, the interposer 106 includes columnar interconnects which may be fabricated by etching a conductive member such as copper foil, for example. In one application, the pitch or center to center spacing of the columnar interconnects may be defined by masking techniques to provide an interconnect pitch suitable for a particular application. In yet another aspect, etching rates may be controlled to provide height to width aspect ratios of the columnar interconnects which are suitable for various applications.
摘要翻译：在一个实施例中，组装包装堆叠包括第一集成电路封装和第二集成电路封装，其使用中介层机械和电连接。在一个实施例中，插入器106包括可以通过例如蚀刻诸如铜箔的导电构件来制造的柱状互连。在一个应用中，柱状互连的间距或中心到中心间隔可以通过掩模技术来定义，以提供适合于特定应用的互连间距。在另一方面，可以控制蚀刻速率以提供适合于各种应用的柱状互连的高宽比长宽比。

28. 发明授权

US07402515B2 Method of forming through-silicon vias with stress buffer collars and resulting devices 有权
公开(公告)号：US07402515B2
公开(公告)日：2008-07-22
申请号：US11169595
申请日：2005-06-28
申请人： Leonel R. Arana , Devendra Natekar , Michael Newman , Charan K. Gurumurthy
发明人： Leonel R. Arana , Devendra Natekar , Michael Newman , Charan K. Gurumurthy
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76898 , H01L2224/13 , H01L2924/1461 , H01L2924/00
摘要： A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed.

29. 发明申请

US20070000592A1 Apparatus and method to operate on one or more attach sites in die package assembly 审中-公开
标题翻译：在模具封装组件中的一个或多个附着位置上操作的装置和方法
公开(公告)号：US20070000592A1
公开(公告)日：2007-01-04
申请号：US11172029
申请日：2005-06-29
申请人： Farokh Fares , Erming Luo , Devendra Natekar
发明人： Farokh Fares , Erming Luo , Devendra Natekar
IPC分类号： B32B37/12 , B32B38/00 , B32B37/06
CPC分类号： H01L24/93 , H01L24/81 , H01L2224/16 , H01L2224/81801 , H01L2224/83192 , H01L2924/01005 , H01L2924/01006 , H01L2924/014 , H01L2924/10253 , Y10T156/1089 , Y10T156/1702 , Y10T156/1744 , Y10T156/1768 , Y10T156/1798 , H01L2924/00
摘要： An assembly arrangement includes an assembly head having plural nozzles. The assembly head is designed to operate on a group of attach sites of a substrate at substantially the same time and is designed to be moveable relative to the substrate to allow the plural nozzles to successively operate on different groups of attach sites of the substrate.
摘要翻译：组装装置包括具有多个喷嘴的组装头。组装头设计成在基本上相同的时间在一组基底的附着位置上操作，并被设计成相对于基底可移动，以允许多个喷嘴在衬底的不同组的附着位置上连续地操作。

30. 发明申请

US20060046433A1 Thinning semiconductor wafers 审中-公开
标题翻译：薄化半导体晶圆
公开(公告)号：US20060046433A1
公开(公告)日：2006-03-02
申请号：US10925775
申请日：2004-08-25
申请人： Terry Sterrett , Leonel Arana , Devendra Natekar
发明人： Terry Sterrett , Leonel Arana , Devendra Natekar
IPC分类号： H01L21/463
CPC分类号： H01L21/02013 , H01L21/6835 , H01L21/6836 , H01L2221/68327 , H01L2221/6834 , H01L2221/68363
摘要： Wafer thinning may be accomplished by grinding while the wafer is held in the fixture. The fixture may have a series of protrusions that form an interference fit with surface features extending outwardly from the non-thinned surface of the wafer to be thinned. In some embodiments, a releasable adhesive may be utilized to augment the interference effect. Also, in some embodiments, openings in a shape memory material may be utilized that, upon heating, more firmly engage the bumps on the wafer to be thinned.
摘要翻译：晶片变薄可以通过在晶片保持在固定装置中的同时进行研磨来实现。夹具可以具有一系列突起，其形成与要被变薄的晶片的非变薄表面向外延伸的表面特征的过盈配合。在一些实施方案中，可以使用可释放粘合剂来增加干扰效应。此外，在一些实施例中，可以利用形状记忆材料中的开口，其在加热时更牢固地接合要稀释的晶片上的凸块。

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