专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US5905679A Semiconductor memory device clamping the overshoot and undershoot of input signal by circuit with PN junction 失效
标题翻译：半导体存储器件通过具有PN结的电路钳位输入信号的过冲和下冲
公开(公告)号：US5905679A
公开(公告)日：1999-05-18
申请号：US45567
申请日：1998-03-23
申请人： Yasuhiko Tsukikawa
发明人： Yasuhiko Tsukikawa
IPC分类号： H01L27/108 , H01L21/8242 , H01L27/092 , G11C7/00
CPC分类号： H01L27/0928
摘要： An input signal applied to a terminal receiving an external signal (e.g. a data input/output terminal DQj) is transmitted by an input signal line. A p well formed in a main surface of a p substrate is electrically isolated from the p substrate by an n well and a triple n well. The p well and the n well receive a potential level of the signal input line. An n diffusion layer is formed in a main surface of the p well and receives an external power supply potential Vdd.
摘要翻译：通过输入信号线发送施加到接收外部信号的终端（例如，数据输入/输出端子DQj）的输入信号。在p基板的主表面中形成的p阱通过n阱和三重n阱与p衬底电隔离。 p阱和n阱接收信号输入线的电位电平。在p阱的主表面中形成n个扩散层，并接收外部电源电位Vdd。

22. 发明授权

US5715212A Semiconductor memory device comprising address transition detecting circuit having stable response characteristic for address signal conversion 失效
标题翻译：半导体存储器件包括具有稳定的地址信号转换响应特性的地址转换检测电路
公开(公告)号：US5715212A
公开(公告)日：1998-02-03
申请号：US652038
申请日：1996-05-23
申请人： Susumu Tanida , Yasuhiko Tsukikawa
发明人： Susumu Tanida , Yasuhiko Tsukikawa
IPC分类号： G11C11/41 , G11C8/18 , G11C11/408 , G11C8/00
CPC分类号： G11C8/18
摘要： In an address transition detecting circuit, signal conversion detecting circuits output complementary time difference signals which are inverted in response to potential level changes of corresponding address lines respectively. Waveform shaping one-shot pulse generating circuits receive corresponding complementary time difference signals and output one-shot pulse signals of prescribed time widths. A waveform composing circuit outputs an ATD signal of a prescribed pulse length in response to activation of any one-shot pulse signal. Therefore, the lengths of the one-shot pulses outputted from the waveform shaping one-shot pulse generating circuits remain unchanged even if the potential level of any signal line is abruptly converted, and an ATD signal of a constant pulse length is regularly outputted.
摘要翻译：在地址转换检测电路中，信号转换检测电路分别响应于相应地址线的电位电平变化而输出互补时差信号。波形整形单脉冲发生电路接收相应的互补时差信号并输出规定时间宽度的单触发脉冲信号。波形合成电路响应于任何单触发脉冲信号的激活而输出规定脉冲长度的ATD信号。因此，即使任何信号线的电位电平突然转换，从波形整形单脉冲发生电路输出的单触发脉冲的长度保持不变，并且定期输出恒定脉冲长度的ATD信号。

23. 发明授权

US5696726A Complementary differential amplifier in which direct current amplification gain can be set arbitrarily and semiconductor memory divice using the same 失效
标题翻译：可以任意设置直流放大增益的互补差分放大器和使用相同的半导体存储器件
公开(公告)号：US5696726A
公开(公告)日：1997-12-09
申请号：US787334
申请日：1997-01-27
申请人： Yasuhiko Tsukikawa
发明人： Yasuhiko Tsukikawa
IPC分类号： G11C11/409 , G11C7/06 , G11C11/407 , G11C7/00 , H03F3/45
CPC分类号： G11C7/062
摘要： P channel MOS transistors P11 and P12 have their gates cross-connected to their drains. P channel MOS transistors P13 and P14 each having its gate and its drain diode-connected to each other are respectively connected in parallel to transistors P11 and P12. N channel MOS transistors N15 and N16 drive transistors P11 to P14 with current values corresponding to input signals IN and /IN. If transistors P11-P14 have the same gate length, transistors P11 and P12 have the same gate width, and transistors P13 and P14 have the same gate width, the DC amplification factor of an internal differential amplifying circuit 1100 of a first stage can be set to a desired value by the ratio of a gate width of P13 to a gate width of P11. Internal outputs from nodes to which the drains of P11 and P12 are respectively connected are input to an internal differential amplifying circuit 1200 of the following stage.
摘要翻译： P沟道MOS晶体管P11和P12的栅极与其漏极交叉连接。分别与栅极和漏极二极管相连的P沟道MOS晶体管P13和P14分别与晶体管P11和P12并联连接。 N沟道MOS晶体管N15和N16驱动具有对应于输入信号IN和/ IN的电流值的晶体管P11至P14。如果晶体管P11-P14具有相同的栅极长度，则晶体管P11和P12具有相同的栅极宽度，并且晶体管P13和P14具有相同的栅极宽度，可以设置第一级的内部差分放大电路1100的DC放大系数通过P13的栅极宽度与P11的栅极宽度的比率达到期望值。分别连接到P11和P12的漏极的节点的内部输出被输入到后级的内部差分放大电路1200。

24. 发明授权

US5394365A Charge pump circuit having an improved charge pumping efficiency 失效
标题翻译：电荷泵电路具有改进的电荷泵送效率
公开(公告)号：US5394365A
公开(公告)日：1995-02-28
申请号：US45069
申请日：1993-04-12
申请人： Yasuhiko Tsukikawa
发明人： Yasuhiko Tsukikawa
IPC分类号： H01L21/8238 , G11C5/14 , G11C11/408 , H01L27/02 , H01L27/092 , H02M3/07
CPC分类号： H02M3/073 , G11C5/145 , G11C5/146 , H01L27/0222 , H01L2924/0002 , H02M2003/078
摘要： A charge pump circuit includes a P channel field effect transistor, a diode-connected N channel field effect transistor between a first node and a second node. The P channel field effect transistor operates in response to a first clock signal applied through a first capacitor to discharge the first node to a ground potential. The first node receives a second clock signal through a second capacitor. Negative electric charges are pumped out to the second node. A negative bias voltage is generated from the second node with an improved efficiency and reliability.
摘要翻译：电荷泵电路包括P沟道场效应晶体管，在第一节点和第二节点之间的二极管连接的N沟道场效应晶体管。 P沟道场效应晶体管响应于通过第一电容器施加的第一时钟信号而工作，以将第一节点放电到地电位。第一节点通过第二电容器接收第二时钟信号。负电荷被抽出到第二节点。从第二节点产生负偏压，效率和可靠性得到提高。

25. 发明授权

US07288965B2 Semiconductor device and level conversion circuit 失效
公开(公告)号：US07288965B2
公开(公告)日：2007-10-30
申请号：US11642726
申请日：2006-12-21
申请人： Kyoji Yamasaki , Yasuhiko Tsukikawa
发明人： Kyoji Yamasaki , Yasuhiko Tsukikawa
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/012 , H03K17/223
摘要： A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.

26. 发明授权

US07072204B2 Semiconductor memory device having dummy word line 失效
标题翻译：具有虚拟字线的半导体存储器件
公开(公告)号：US07072204B2
公开(公告)日：2006-07-04
申请号：US11131384
申请日：2005-05-18
申请人： Yasuhiko Tsukikawa , Takashi Ito
发明人： Yasuhiko Tsukikawa , Takashi Ito
IPC分类号： G11C11/24
CPC分类号： H01L27/10882 , G11C7/18 , G11C11/405 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10814
摘要： Each cell unit has a cell plate electrically isolated from the cell plates in the other cell units.
摘要翻译：每个电池单元具有与其它电池单元中的电池板电隔离的电池板。

27. 发明申请

US20050068062A1 Semiconductor device and level conversion circuit 失效
标题翻译：半导体器件和电平转换电路
公开(公告)号：US20050068062A1
公开(公告)日：2005-03-31
申请号：US10947257
申请日：2004-09-23
申请人： Kyoji Yamasaki , Yasuhiko Tsukikawa
发明人： Kyoji Yamasaki , Yasuhiko Tsukikawa
IPC分类号： H03K17/16 , H03K3/012 , H03K3/356 , H03K17/22 , H03K19/0185 , H03K19/0175
CPC分类号： H03K3/356113 , H03K3/012 , H03K17/223
摘要： A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.
摘要翻译：电平转换电路，将从接收第一电源电压的第二内部电路输出的信号转换为具有与第一电源电压不同的电压电平的第二电源电压的电平的信号，以将其输出信号施加到第一内部电路设置有用于在第一电源电压被切断时切断通过电平转换电路中的通过电流的路径的机构。

28. 发明授权

US06787859B2 Semiconductor memory device with shortened connection length among memory block, data buffer and data bus 有权
标题翻译：具有缩短存储块，数据缓冲器和数据总线之间连接长度的半导体存储器件
公开(公告)号：US06787859B2
公开(公告)日：2004-09-07
申请号：US10223319
申请日：2002-08-20
申请人： Takashi Itou , Masaki Shimoda , Yasuhiko Tsukikawa
发明人： Takashi Itou , Masaki Shimoda , Yasuhiko Tsukikawa
IPC分类号： H01L2994
CPC分类号： G11C5/025 , G11C7/18
摘要： There is provided a semiconductor memory device including eight memory blocks 20a to 20h, first data bus 22a, and second data bus 22b. The eight memory blocks are arranged at respective eight of the total nine areas 11 to 19 defined in a three rows by three columns matrix except for a center area 19. A first data bus 22a linearly extends between memory blocks in the first and second row of the matrix. A second data bus 22b linearly extends between memory blocks in the second and third row of the matrix. The eight memory blocks includes a first group of the four memory blocks arranged adjacent the first data bus and connected to the first data bus and a second group of the four memory blocks arranged adjacent the second data bus and connected to the second data bus.
摘要翻译：提供了包括八个存储块20a至20h，第一数据总线22a和第二数据总线22b的半导体存储器件。八个存储块被布置在除了中心区域19之外以三行×三列矩阵定义的总共九个区域11至19中的相应八个。第一数据总线22a在第一和第二行中的存储块之间线性地延伸矩阵。第二数据总线22b在矩阵的第二和第三行中的存储块之间线性地延伸。八个存储器块包括与第一数据总线相邻布置并连接到第一数据总线的四个存储器块的第一组以及与第二数据总线相邻布置并连接到第二数据总线的四个存储器块的第二组。

29. 发明授权

US06727738B2 Configuration for generating a clock including a delay circuit and method thereof 有权
标题翻译：用于产生包括延迟电路的时钟的配置及其方法
公开(公告)号：US06727738B2
公开(公告)日：2004-04-27
申请号：US09877027
申请日：2001-06-11
申请人： Yasuhiko Tsukikawa
发明人： Yasuhiko Tsukikawa
IPC分类号： H03L700
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , H03L7/0814 , H03L7/0818
摘要： A delay locked loop (DLL) employs a gray code (an alternate code) counter as a delay register. Preventing a carry from arising at more than one bit can minimize skipping of delay time (discontinuous skipping thereof) if a metastable state should occur.
摘要翻译：延迟锁定环（DLL）使用灰色代码（替代代码）计数器作为延迟寄存器。如果发生亚稳态，防止进位超过一个位可能会使延迟时间的跳跃（不连续跳跃）最小化。

30. 发明授权

US06249462B1 Data output circuit that can drive output data speedily and semiconductor memory device including such a data output circuit 失效
标题翻译：能够快速驱动输出数据的数据输出电路和包括这种数据输出电路的半导体存储器件
公开(公告)号：US06249462B1
公开(公告)日：2001-06-19
申请号：US09557867
申请日：2000-04-24
申请人： Koji Tanaka , Jun Nakai , Yasuhiko Tsukikawa , Mikio Asakura
发明人： Koji Tanaka , Jun Nakai , Yasuhiko Tsukikawa , Mikio Asakura
IPC分类号： G11C1604
CPC分类号： G11C7/1069 , G11C7/1051 , G11C11/4093
摘要： An output buffer includes a pull up transistor of N type field effect to charge a data output terminal by an external power supply potential Vdd in a high level data output operation, and a pull down transistor of N type field effect to discharge the data output terminal to a ground potential Vss in a low level data output operation. The substrate potential of the pull up NMOS transistor is set to a potential of a level higher than the normal case in a high level data output operation. As a result, the output buffer can speedily charge the data terminal in a high level data output operation.
摘要翻译：输出缓冲器包括N型场效应的上拉晶体管，用于在高电平数据输出操作中由外部电源电位Vdd对数据输出端子充电;以及N型场效应的下拉晶体管，以对数据输出端子到低电平数据输出操作中的地电位Vss。在高电平数据输出操作中，上拉NMOS晶体管的衬底电位被设置为高于正常情况的电平。结果，输出缓冲器可以在高电平数据输出操作中对数据终端进行快速充电。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式