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21. 发明授权

US08420489B2 High-performance semiconductor device and method of manufacturing the same 有权
标题翻译：高性能半导体器件及其制造方法
公开(公告)号：US08420489B2
公开(公告)日：2013-04-16
申请号：US12996809
申请日：2010-06-25
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L21/336
CPC分类号： H01L29/4966 , H01L21/26586 , H01L29/51 , H01L29/66537 , H01L29/66545 , H01L29/78
摘要： A method of manufacturing a semiconductor device, wherein thermal annealing of the source/drain regions is performed before reverse Halo implantation to form a reverse Halo implantation region. The method comprises: removing the dummy gate to expose the gate dielectric layer, so as to form an opening; performing reverse Halo implantation on the substrate via the opening, so as to form a reverse Halo implantation region in the channel of the device; activating the dopants in the reverse Halo implantation region by annealing; and performing subsequent device processing. Deterioration of the gate stack due to the reverse Halo ions implantation may be avoided by the present invention, such that the reverse Halo ions implantation may be applied to the device with a metal gate stack, and the short channel effects may be alleviated and controlled, thereby the performance of the device is enhanced.
摘要翻译：一种制造半导体器件的方法，其中在反向光晕注入之前进行源极/漏极区域的热退火以形成反向光晕注入区域。该方法包括：去除虚拟栅极以露出栅极电介质层，以形成开口; 经由开口在衬底上进行反向光晕注入，以在器件的沟道中形成反向光晕注入区域; 通过退火激活反向卤素注入区域中的掺杂剂; 并执行后续的设备处理。通过本发明可以避免由于反向卤素离子注入引起的栅极堆叠的劣化，使得可以用金属栅极叠层将相反的Halo离子注入施加到器件，并且可以减轻和控制短沟道效应，从而增强了设备的性能。

22. 发明申请

US20130082354A1 Semiconductor Structure and Method for Manufacturing the Same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130082354A1
公开(公告)日：2013-04-04
申请号：US13580966
申请日：2012-05-14
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/36 , H01L21/20
CPC分类号： H01L29/785 , H01L21/7624 , H01L21/823431 , H01L21/845 , H01L29/66795
摘要： The present invention provides a method for manufacturing a semiconductor structure, comprising the steps of: providing a semiconductor substrate, forming an insulating layer on the semiconductor substrate, and forming a semiconductor base layer on the insulating layer; forming a sacrificial layer and a spacer surrounding the sacrificial layer on the semiconductor base layer, and etching the semiconductor base layer by taking the spacer as a mask to form a semiconductor body; forming a dielectric film on sidewalls of the semiconductor body; removing the sacrificial layer and the semiconductor body located under the sacrificial layer to form a first semiconductor fin and a second semiconductor fin; and forming a retrograde doped well structure on the inner walls of the first semiconductor fin and the second semiconductor fin, wherein the inner walls thereof are opposite to each other. Correspondingly, the present invention further provides a semiconductor structure. In the present invention, a retrograde doped well structure is formed on the sidewalls of the two semiconductor fins that are opposite to each other, so that the width of the source/drain depletion layer may be effectively reduced, and thereby the short channel effect is reduced.
摘要翻译：本发明提供一种制造半导体结构的方法，包括以下步骤：提供半导体衬底，在半导体衬底上形成绝缘层，并在绝缘层上形成半导体基底层; 在所述半导体基底层上形成包围所述牺牲层的牺牲层和间隔物，并且通过以所述间隔物作为掩模来蚀刻所述半导体基底层以形成半导体本体; 在所述半导体主体的侧壁上形成电介质膜; 去除位于牺牲层下面的牺牲层和半导体本体以形成第一半导体鳍片和第二半导体鳍片; 以及在所述第一半导体翅片和所述第二半导体翅片的内壁上形成逆向掺杂的阱结构，其中所述内壁彼此相对。相应地，本发明还提供一种半导体结构。在本发明中，在两个相互相对的两个半导体鳍片的侧壁上形成逆向掺杂阱结构，从而可以有效地减小源/漏耗尽层的宽度，从而短沟道效应为减少

23. 发明申请

US20130069041A1 METHOD FOR MANUFACTURING GRAPHENE NANO-RIBBON, MOSFET AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：制造石墨纳米薄膜的方法，MOSFET及其制造方法
公开(公告)号：US20130069041A1
公开(公告)日：2013-03-21
申请号：US13510390
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/20 , H01L21/336 , H01L29/775 , B82Y99/00 , B82Y40/00
CPC分类号： H01L21/0242 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/02422 , H01L21/02488 , H01L21/02491 , H01L21/02507 , H01L21/02527 , H01L21/02639 , H01L29/0673 , H01L29/1606 , H01L29/2003 , H01L29/66742 , H01L29/775 , H01L29/78684 , H01L29/78696
摘要： A MOSFET with a graphene nano-ribbon, and a method for manufacturing the same are provided. The MOSFET comprises an insulating substrate; and an oxide protection layer on the insulating substrate. At least one graphene nano-ribbon is embedded in the oxide protection layer and has a surface which is exposed at a side surface of the oxide protection layer. A channel region is provided in each of the at least one graphene nano-ribbon. A source region and a drain regions are provided in each of the at least one graphene nano-ribbon. The channel region is located between the source region and the drain region. A gate dielectric is positioned on the at least one graphene nano-ribbon. A gate conductor on the gate dielectric. A source and drain contacts contact the source region and the drain region respectively on the side surface of the oxide protection layer.
摘要翻译：提供了具有石墨烯纳米带的MOSFET及其制造方法。 MOSFET包括绝缘基板; 和绝缘基板上的氧化物保护层。至少一个石墨烯纳米带被嵌入在氧化物保护层中并且具有暴露在氧化物保护层的侧表面的表面。在所述至少一个石墨烯纳米带的每个中设置有沟道区。在所述至少一个石墨烯纳米带的每一个中设置源极区和漏极区。沟道区位于源区和漏区之间。栅电介质位于至少一个石墨烯纳米带上。栅极电介质上的栅极导体。源极和漏极触点分别在氧化物保护层的侧表面上接触源极区域和漏极区域。

24. 发明申请

US20130049138A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130049138A1
公开(公告)日：2013-02-28
申请号：US13634266
申请日：2011-11-18
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L21/823431
摘要： The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a semiconductor layer; a first fin being formed by patterning the semiconductor layer; and a second fin being formed by patterning the semiconductor layer, wherein: top sides of the first and second fins have the same height; bottom sides of the first and second fins adjoin the semiconductor layer; and the second fin is higher than the first fin. According to the present disclosure, a plurality of semiconductor devices with different dimensions can be integrated on the same wafer. As a result, manufacturing process can be shortened and manufacturing cost can be reduced. Furthermore, devices with different driving capabilities can be provided.
摘要翻译：本发明提供一种半导体器件及其制造方法。半导体器件包括：半导体层; 通过图案化半导体层形成第一鳍片; 并且通过图案化半导体层形成第二鳍片，其中：第一鳍片和第二鳍片的顶侧具有相同的高度; 第一和第二散热片的底面邻接半导体层; 第二鳍高于第一鳍。根据本公开，可以将多个具有不同尺寸的半导体器件集成在同一晶片上。结果，可以缩短制造工序，降低制造成本。此外，可以提供具有不同驱动能力的装置。

25. 发明申请

US20130032777A1 Semiconductor Device and Manufacturing Method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130032777A1
公开(公告)日：2013-02-07
申请号：US13376237
申请日：2011-08-05
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/06 , H01L21/20 , B82Y99/00 , B82Y40/00
CPC分类号： H01L29/45 , B82Y10/00 , H01L29/1606 , H01L29/42316 , H01L29/66431 , H01L29/7781 , H01L29/78618 , H01L29/78684 , H01L51/0048 , H01L51/0562
摘要： The present invention discloses a semiconductor device and a manufacturing method thereof. The method comprises the steps of providing a substrate on which a graphene layer or carbon nanotube layer is formed; exposing part of the graphene layer or carbon nanotube layer after forming a gate structure on the graphene layer or carbon nanotube layer, wherein the gate structure comprises a gate stack, a spacer and a cap layer, the cap layer is located on the gate stack, and the spacer surrounds the gate stack and the cap layer; epitaxially growing a semiconductor layer on the exposed graphene layer or carbon nanotube layer; and forming a metal contact layer on the semiconductor layer. In the present invention, the semiconductor layer is formed on the graphene layer or carbon nanotube layer, and then the metal contact layer is formed on the semiconductor layer, instead of forming the metal contact layer directly from the graphene layer or carbon nanotube layer. This facilitates to form the self-aligned source and drain contact plugs.
摘要翻译：本发明公开了一种半导体器件及其制造方法。该方法包括提供其上形成有石墨烯层或碳纳米管层的基板的步骤; 在石墨烯层或碳纳米管层上形成栅极结构之后暴露部分石墨烯层或碳纳米管层，其中栅极结构包括栅极堆叠，间隔物和覆盖层，盖层位于栅极叠层上，并且所述间隔件围绕所述栅极堆叠和所述盖层; 在暴露的石墨烯层或碳纳米管层上外延生长半导体层; 以及在所述半导体层上形成金属接触层。在本发明中，在石墨烯层或碳纳米管层上形成半导体层，然后在半导体层上形成金属接触层，而不是直接从石墨烯层或碳纳米管层形成金属接触层。这有助于形成自对准的源极和漏极接触插头。

26. 发明申请

US20130015497A1 SOURCE/DRAIN REGION, CONTACT HOLE AND METHOD FOR FORMING THE SAME 有权
标题翻译：源/排水区，接触孔及其形成方法
公开(公告)号：US20130015497A1
公开(公告)日：2013-01-17
申请号：US13119074
申请日：2011-02-18
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/768 , H01L23/48
CPC分类号： H01L29/0847 , H01L21/76805 , H01L21/823807 , H01L21/823814 , H01L29/66636 , H01L29/78
摘要： An S/D region including a first region and a second region is provided. The first region is located, with at least a partial thickness, in the substrate. The second region is formed on the first region and made of a material different from that of the first region. A method for forming an S/D region is further provided, and the method includes: forming trenches at both sides of a gate stack structure in a substrate; forming a first semiconductor layer, wherein at least a part of the first semiconductor layer is filled into the trenches; and forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer is made of a material different from that of the first semiconductor layer. A contact hole and a forming method thereof are also provided which may increase the contact area between a contact hole and a contact region, and reduce the contact resistance.
摘要翻译：提供包括第一区域和第二区域的S / D区域。第一区域在衬底中具有至少部分厚度。第二区域形成在第一区域上并且由与第一区域不同的材料制成。还提供了形成S / D区域的方法，该方法包括：在基板中的栅叠层结构的两侧形成沟槽; 形成第一半导体层，其中所述第一半导体层的至少一部分被填充到所述沟槽中; 以及在所述第一半导体层上形成第二半导体层，其中所述第二半导体层由与所述第一半导体层不同的材料制成。还提供接触孔及其形成方法，其可以增加接触孔和接触区域之间的接触面积，并降低接触电阻。

27. 发明申请

US20130001691A1 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130001691A1
公开(公告)日：2013-01-03
申请号：US13381075
申请日：2011-08-25
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/772 , H01L21/283
CPC分类号： H01L29/41733 , H01L21/76816 , H01L21/76882 , H01L21/76897 , H01L23/485 , H01L29/458 , H01L29/66636 , H01L29/66772 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a semiconductor structure, which comprises: providing an SOI substrate, and forming a gate structure on the SOI substrate; etching an SOI layer and a BOX layer of the SOI substrates on both sides of the gate structure, so as to form trenches exposing the BOX layer and extending partially into the BOX layer; forming metal sidewall spacers on sidewalls of the trenches, wherein the metal sidewall spacers is in contact with the SOI layer under the gate structure; forming an insulating layer filling partially the trenches, and forming a dielectric layer to cover the gate structure and the insulating layer; etching the dielectric layer to form first contact through holes that expose at least partially the insulating layer, and etching the insulating layer from the first contact through holes to form second contact through holes that expose at least partially the metal sidewall spacer; filling the first contact through holes and the second contact through holes to form contact vias, which are in contact with the metal sidewall spacers. The method provided by the present invention is capable of improving performance of semiconductor devices and alleviating manufacturing difficulty at the mean time.
摘要翻译：本发明提供一种制造半导体结构的方法，其包括：提供SOI衬底，并在SOI衬底上形成栅极结构; 在栅极结构的两侧蚀刻SOI衬底的SOI层和BOX层，以形成露出BOX层并部分延伸到BOX层的沟槽; 在所述沟槽的侧壁上形成金属侧壁间隔物，其中所述金属侧壁间隔物与所述栅极结构下的所述SOI层接触; 形成部分填充沟槽的绝缘层，形成覆盖栅结构和绝缘层的电介质层; 蚀刻所述介电层以形成至少部分地暴露所述绝缘层的第一接触通孔，以及从所述第一接触通孔蚀刻所述绝缘层以形成至少部分地暴露所述金属侧壁间隔物的第二接触通孔; 通过孔和第二接触通孔填充第一接触件以形成与金属侧壁间隔件接触的接触通孔。本发明提供的方法能够提高半导体装置的性能，同时能够减轻制造难度。

28. 发明授权

US08343818B2 Method for forming retrograded well for MOSFET 有权
公开(公告)号：US08343818B2
公开(公告)日：2013-01-01
申请号：US12687287
申请日：2010-01-14
申请人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
IPC分类号： H01L21/84
CPC分类号： H01L21/187 , H01L21/6835 , H01L21/84 , H01L27/12 , H01L29/1083 , H01L2221/6835 , H01L2221/68368
摘要： A method of forming an electrical device is provided that includes forming at least one semiconductor device on a first semiconductor layer of the SOI substrate. A handling structure is formed contacting the at least one semiconductor device and the first semiconductor layer. A second semiconductor layer and at least a portion of the dielectric layer of the SOI substrate are removed to provide a substantially exposed surface of the first semiconductor layer. A retrograded well may be formed by implanting dopant through the substantially exposed surface of the first semiconductor layer into a first thickness of the semiconductor layer that extends from the substantially exposed surface of the semiconductor layer, wherein a remaining thickness of the semiconductor layer is substantially free of the retrograded well dopant. The retrograded well may be laser annealed.

29. 发明申请

US20120292766A2 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：其半导体结构及其制造方法
公开(公告)号：US20120292766A2
公开(公告)日：2012-11-22
申请号：US12990990
申请日：2010-09-19
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/522 , H01L21/32051 , H01L21/76823 , H01L21/76838 , H01L21/76873 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor structure and a manufacturing method thereof. The method comprises: providing a semiconductor substrate comprising semiconductor devices; depositing a copper diffusion barrier layer on the semiconductor substrate; forming a copper composite layer on the copper diffusion barrier layer; decomposing the copper composite at corresponding positions, where copper interconnection is to be formed, into copper according to the shape of the copper interconnection; and etching off the undecomposed copper composite and the copper diffusion barrier layer underneath, to interconnect the semiconductor devices. The present invention is adaptive for manufacturing interconnection in integrated circuits.
摘要翻译：本发明提供一种半导体结构及其制造方法。该方法包括：提供包括半导体器件的半导体衬底; 在所述半导体衬底上沉积铜扩散阻挡层; 在铜扩散阻挡层上形成铜复合层; 根据铜互连的形状，将要形成铜互连的相应位置处的铜复合物分解成铜; 并且在下面蚀刻未分解的铜复合物和铜扩散阻挡层，以使半导体器件互连。本发明适用于制造集成电路中的互连。

30. 发明申请

US20120264262A1 Method for forming semiconductor structure 有权
标题翻译：半导体结构形成方法
公开(公告)号：US20120264262A1
公开(公告)日：2012-10-18
申请号：US13381014
申请日：2011-04-18
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/823828 , H01L29/7833 , H01L29/7847 , H01L29/7848
摘要： The invention relates to a method for forming a semiconductor structure, comprising: providing a semiconductor substrate which comprises a dummy gate formed thereon, a spacer surrounding the dummy gate, source and drain regions formed on two sides of the dummy gate, respectively, and a channel region formed in the semiconductor substrate and below the dummy gate; removing the dummy gate to form a gate opening; forming a stressed material layer in the gate opening; performing an annealing to the semiconductor substrate, the stressed material layer having tensile stress characteristics during the annealing; removing the stressed material layer in the gate opening; and forming a gate in the gate opening. By the above steps, the stress memorization technique can be applied to the pMOSFET.
摘要翻译：本发明涉及一种形成半导体结构的方法，包括：提供包括形成在其上的虚拟栅极的半导体衬底，围绕伪栅极的间隔物，分别形成在虚拟栅极两侧的源区和漏区，以及形成在半导体衬底中并在虚拟栅极之下的沟道区; 去除虚拟门以形成门开口; 在闸门开口处形成应力材料层; 对所述半导体基板进行退火，所述应力材料层在退火时具有拉伸应力特性; 去除闸门开口中的应力材料层; 并在门开口形成门。通过上述步骤，可以将应力记忆技术应用于pMOSFET。

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