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21. 发明授权

US10811493B2 Single event latch-up (SEL) mitigation techniques 有权
公开(公告)号：US10811493B2
公开(公告)日：2020-10-20
申请号：US16109273
申请日：2018-08-22
申请人： Xilinx, Inc.
发明人： James Karp , Michael J. Hart
IPC分类号： H01L29/06 , H01L27/092 , H01L27/06
摘要： Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a semiconductor structure includes a semiconductor substrate, a p-type transistor having p+ source/drain regions disposed in a n-doped region in the semiconductor substrate, an n-type transistor having n+ source/drain regions disposed in a p-doped region in the semiconductor substrate, a n+ guard ring disposed in the n-doped region and laterally around the p+ source/drain regions of the p-type transistor, and a p+ guard ring disposed laterally around the n-doped region. The p+ guard ring is disposed between the p-type transistor and the n-type transistor.

22. 发明授权

US10497677B1 ESD protection in a stacked integrated circuit assembly 有权
公开(公告)号：US10497677B1
公开(公告)日：2019-12-03
申请号：US15429112
申请日：2017-02-09
申请人： Xilinx, Inc.
发明人： James Karp
IPC分类号： H01L25/065 , H01L27/02 , H01L25/00
CPC分类号： H01L25/0657 , H01L25/50 , H01L27/0255 , H01L27/0288 , H01L27/0292 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06568
摘要： An example integrated circuit (IC) assembly includes: a substrate, and a first IC die stacked on a second IC die, a stack of the first IC die and the second IC die mounted to the substrate. The first IC die includes an active side, a backside, a plurality of through-silicon vias (TSVs) exposed on the backside, an electrostatic discharge (ESD) circuit on the active side, and metallization on the active side. The metallization includes a first plurality of metal layers disposed on the active side and a second plurality of metal layers disposed on the first plurality of metal layers, each of the second plurality of metal layers thicker than each of the first plurality of metal layers. The metallization further includes a U-route that electrically couples a first TSV of the plurality of TSVs to the ESD circuit, the U-route including a conductive path through the second plurality of metal layers.

23. 发明授权

US09831218B1 Wafer to wafer stacking 有权
公开(公告)号：US09831218B1
公开(公告)日：2017-11-28
申请号：US15480258
申请日：2017-04-05
申请人： Xilinx, Inc.
发明人： James Karp , Michael J. Hart
IPC分类号： H01L25/065 , H01L25/00
CPC分类号： H01L25/0657 , H01L23/60 , H01L25/50 , H01L2225/06513 , H01L2225/06572
摘要： Embodiments herein describe techniques for wafer to wafer stacking of integrated circuit chips (e.g., dice) to form stacked IC devices. In one example, a stacked IC device is provided that includes a first wafer, a second wafer, and first conductive bridge. The second wafer is stacked on and secured to the first wafer. The second wafer has a plurality of IC dice that are communicatively coupled to a plurality of IC dice formed on the first wafer. The first conductive bridge has a first end that is sandwiched between the first and second wafers. The first conductive bridge shorts exposed pads of dice formed in the exclusion zones of the first and second wafers.

24. 发明授权

US09013844B2 Circuit for and method of enabling the discharge of electric charge in an integrated circuit 有权
标题翻译：能够在集成电路中放电的电路和方法
公开(公告)号：US09013844B2
公开(公告)日：2015-04-21
申请号：US13741619
申请日：2013-01-15
申请人： Xilinx, Inc.
发明人： James Karp
IPC分类号： H02H9/04 , H01L27/06 , H01L27/02
CPC分类号： H02H9/044 , H01L27/0251 , H01L27/0255 , H01L27/0629
摘要： A circuit for enabling the discharge of electric charge in an integrated circuit is described. The circuit comprises an input/output pad coupled to a first node; a first diode coupled between the first node and a ground node; a transistor coupled in parallel with the first diode between the first node and ground node; and a resistor coupled between a body portion of the transistor and the ground node. A method of enabling the discharge of electric charge is also described.
摘要翻译：描述了用于使能集成电路中的电荷放电的电路。该电路包括耦合到第一节点的输入/输出垫; 耦合在第一节点和接地节点之间的第一二极管; 与所述第一节点和所述接地节点之间的所述第一二极管并联耦合的晶体管; 以及耦合在晶体管的主体部分和接地节点之间的电阻器。还描述了能够进行电荷放电的方法。

25. 发明申请

US20140145293A1 INTEGRATED CIRCUIT HAVING IMPROVED RADIATION IMMUNITY 有权
标题翻译：具有改善辐射免疫力的集成电路
公开(公告)号：US20140145293A1
公开(公告)日：2014-05-29
申请号：US13686553
申请日：2012-11-27
申请人： Xilinx, Inc.
发明人： Praful Jain , James Karp , Michael J. Hart
IPC分类号： H01L23/552 , H01L21/02
CPC分类号： H01L23/552 , G11C11/4125 , H01L21/02697 , H01L27/0207 , H01L27/1104 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; a P-well formed on the substrate and having N-type transistors of a memory cell; and an N-well formed on the substrate and having P-type transistors of the memory cell; wherein the N-well has minimal dimensions for accommodating the P-type transistors.
摘要翻译：描述了具有改善的辐射抗扰性的集成电路。集成电路包括基板; 在衬底上形成的P阱，并具有存储单元的N型晶体管; 和形成在衬底上并具有存储单元的P型晶体管的N阱; 其中所述N阱具有用于容纳所述P型晶体管的最小尺寸。

26. 发明授权

US11043484B1 Method and apparatus of package enabled ESD protection 有权
公开(公告)号：US11043484B1
公开(公告)日：2021-06-22
申请号：US16362134
申请日：2019-03-22
申请人： Xilinx, Inc.
发明人： Hong Shi , James Karp , Siow Chek Tan , Martin L. Voogel , Mohsen H. Mardi , Suresh Ramalingam , David M. Mahoney
IPC分类号： H01L27/02 , G01R1/04 , H01L25/065 , H01L23/498
摘要： Techniques for electrostatic discharge (ESD) protection in integrated circuit (IC) chip packages methods for testing the same are described that are configured to directs the risk of ESD events through ground and power interconnects preferentially over I/O interconnects to enhance ESD protection in chip packages. In one example, a chip package is provided that includes an IC die, a substrate, and a plurality of interconnects. The plurality of interconnects are exposed on a side of the substrate opposite the IC die. The interconnects provide terminations for substrate circuitry formed within the substrate. At least one of the last 5 interconnects of the plurality of interconnects respectively comprising rows and columns of interconnects disposed along the edges of the substrate that closest to each corner of substrate project farther from the substrate than interconnects within those rows and columns that are configured as I/O interconnects.

27. 发明授权

US10861848B2 Single event latch-up (SEL) mitigation techniques 有权
公开(公告)号：US10861848B2
公开(公告)日：2020-12-08
申请号：US16110894
申请日：2018-08-23
申请人： Xilinx, Inc.
发明人： Michael J. Hart , James Karp , Mohammed Fakhruddin , Pierre Maillard
IPC分类号： H01L27/06 , H01L27/02 , H01L49/02 , H01L29/73 , H01L29/78
摘要： Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a circuit includes a semiconductor substrate, a first transistor, a second transistor, and a ballast resistor. The semiconductor substrate comprises a p-doped region and an n-doped region. The first transistor comprises an n+ doped source region disposed in the p-doped region of the semiconductor substrate. The second transistor comprises a p+ doped source region disposed in the n-doped region of the semiconductor substrate. The p+ doped source region, the n-doped region, the p-doped region, and the n+ doped source region form a PNPN structure. The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node.

28. 发明申请

US20200066837A1 SINGLE EVENT LATCH-UP (SEL) MITIGATION TECHNIQUES 审中-公开
公开(公告)号：US20200066837A1
公开(公告)日：2020-02-27
申请号：US16109273
申请日：2018-08-22
申请人： Xilinx, Inc.
发明人： James Karp , Michael J. Hart
IPC分类号： H01L29/06 , H01L27/06 , H01L27/092
摘要： Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a semiconductor structure includes a semiconductor substrate, a p-type transistor having p+ source/drain regions disposed in a n-doped region in the semiconductor substrate, an n-type transistor having n+ source/drain regions disposed in a p-doped region in the semiconductor substrate, a n+ guard ring disposed in the n-doped region and laterally around the p+ source/drain regions of the p-type transistor, and a p+ guard ring disposed laterally around the n-doped region. The p+ guard ring is disposed between the p-type transistor and the n-type transistor.

29. 发明授权

US10522531B1 Integrated circuit device and method of transmitting data in an integrated circuit device 有权
公开(公告)号：US10522531B1
公开(公告)日：2019-12-31
申请号：US16154647
申请日：2018-10-08
申请人： Xilinx, Inc.
发明人： James Karp
IPC分类号： H01L27/02 , G02B6/42 , H04B10/80 , H01L23/60 , H04B10/60 , H04B10/50 , H04B10/40
摘要： An integrated circuit device is described. The integrated circuit device comprises a substrate having transmitter for receiving a signal to be transmitted to a receiver of the substrate by way of a transmission channel; a first plurality of contacts adapted to receive a first integrated circuit die, wherein a contact of the first plurality of contacts is adapted to receive the signal to be transmitted by the transmitter; a second plurality of contacts adapted to receive a second integrated circuit die, wherein a contact of the second plurality of contacts is adapted to receive the signal transmitted by the transmitter and received by the receiver; a first resistive element coupled between a contact of the first plurality of contacts and the transmitter; and a second resistive element coupled between a contact of the second plurality of contacts and the receiver. A method of transmitting data in an integrated circuit is also described.

30. 发明授权

US09483599B1 Circuit design-specific failure in time rate for single event upsets 有权
标题翻译：电路设计特定的单事件故障时间速率故障
公开(公告)号：US09483599B1
公开(公告)日：2016-11-01
申请号：US14494361
申请日：2014-09-23
申请人： Xilinx, Inc.
发明人： Praful Jain , James Karp
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5022 , G06F17/5054 , G06F17/5081
摘要： Determining a circuit design-specific, failures in time rate for single event upsets for an integrated circuit (IC) includes determining, using a processor, a number of critical interconnect multiplexer bits for a circuit design for a target IC and determining a number of critical look-up table bits for the circuit design. Using the processor, a device vulnerability factor is estimated for the circuit design for the target IC using the number of critical interconnect multiplexer bits and the number of critical look-up table bits. The estimated device vulnerability factor can be stored, e.g., for subsequent comparison with other circuit designs.
摘要翻译：确定电路设计特定的集成电路（IC）的单事件故障的时间速率失败包括使用处理器确定用于目标IC的电路设计的多个关键互连多路复用器位，并确定关键的数量查找表位用于电路设计。使用处理器，使用关键互连复用器位数和关键查找表位数来估计目标IC的电路设计的设备漏洞因素。可以存储估计的设备脆弱性因子，例如用于随后与其他电路设计的比较。

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