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21. 发明授权

US11985061B1 Distributed look-ahead routing in network-on-chip 有权
公开(公告)号：US11985061B1
公开(公告)日：2024-05-14
申请号：US17227258
申请日：2021-04-09
申请人： XILINX, INC.
发明人： Krishnan Srinivasan , Abbas Morshed , Aman Gupta , Sagheer Ahmad
IPC分类号： H04L45/302 , G06F15/78 , H04L45/00 , H04L45/42 , H04L45/745
CPC分类号： H04L45/302 , G06F15/7825 , H04L45/42 , H04L45/566 , H04L45/745 , H04L45/34
摘要： Embodiments herein describe an integrated circuit that includes a network on chip (NoC) where an egress logic block or switch performs a route lookup for a subsequent (e.g., downstream) switch in the NoC (referred to herein as look-ahead routing). After receiving the packet and a port ID from the egress logic block or the switch, the downstream switch knows, without performing route lookup of its own, on which port it should forward the packet. Thus, if the downstream switch performs other functions that are dependent on knowing the destination port (e.g., arbitration or QoS updating), the downstream switch can perform those functions immediately since the port ID was already determined by, and received from, the previous network element.

22. 发明授权

US11636061B2 On-demand packetization for a chip-to-chip interface 有权
公开(公告)号：US11636061B2
公开(公告)日：2023-04-25
申请号：US17464642
申请日：2021-09-01
申请人： XILINX, INC.
发明人： Krishnan Srinivasan , Sagheer Ahmad , Ygal Arbel
IPC分类号： G06F13/42 , G06F13/40
摘要： Embodiments herein describe on-demand packetization where data that is too large to be converted directly into data words (DWs) for a chip-to-chip (C2C) interface are packetized instead. When identifying a protocol word that is larger than the DW of the C2C interface, a protocol layer can perform packetization where a plurality of protocol words are packetized and sent as a transfer. In one embodiment, the protocol layer removes some or all of the control data or signals in the protocol words so that the protocol words no longer exceed the size of the DW. These shortened protocol words can then be mapped to DWs and transmitted as separate packets on the C2C. The protocol layer can then collect the portion of the control data that was removed from the protocol words and transmit this data as a separate packet on the C2C interface.

23. 发明授权

US11580057B2 Subsystem for configuration, security, and management of an adaptive system 有权
公开(公告)号：US11580057B2
公开(公告)日：2023-02-14
申请号：US16666262
申请日：2019-10-28
申请人： Xilinx, Inc.
发明人： Ahmad R. Ansari , Sagheer Ahmad
IPC分类号： G06F15/177 , G06F9/00 , G06F15/78 , G06F1/26 , G06F9/4401 , G06F11/07 , G06F21/57 , G06F21/60 , G06F21/71 , G06F21/76 , G06F21/86
摘要： An integrated circuit (IC) can include a processor system configured to execute program code, a programmable logic, and a platform management controller coupled to the processor system and the programmable logic. The platform management controller is adapted to configure and control the processor system and the programmable logic independently.

24. 发明授权

US11327899B1 Hardware-based virtual-to-physical address translation for programmable logic masters in a system on chip 有权
公开(公告)号：US11327899B1
公开(公告)日：2022-05-10
申请号：US16933923
申请日：2020-07-20
申请人： XILINX, INC.
发明人： Ygal Arbel , Sagheer Ahmad , Gaurav Singh
IPC分类号： G06F12/1027 , H03K19/1776
摘要： An example programmable integrated circuit (IC) includes a processing system having a processor, a master circuit, and a system memory management unit (SMMU). The SMMU includes a first translation buffer unit (TBU) coupled to the master circuit, an address translation (AT) circuit, an AT interface coupled to the AT circuit, and a second TBU coupled to the AT circuit, and programmable logic coupled to the AT circuit in the SMMU through the AT interface.

25. 发明申请

US20210124711A1 SUBSYSTEM FOR CONFIGURATION, SECURITY, AND MANAGEMENT OF AN ADAPTIVE SYSTEM 有权
公开(公告)号：US20210124711A1
公开(公告)日：2021-04-29
申请号：US16666262
申请日：2019-10-28
申请人： Xilinx, Inc.
发明人： Ahmad R. Ansari , Sagheer Ahmad
IPC分类号： G06F15/78 , G06F21/57 , G06F21/76 , G06F1/26 , G06F21/71 , G06F21/60 , G06F21/86 , G06F9/4401 , G06F11/07
摘要： An integrated circuit (IC) can include a processor system configured to execute program code, a programmable logic, and a platform management controller coupled to the processor system and the programmable logic. The platform management controller is adapted to configure and control the processor system and the programmable logic independently.

26. 发明授权

US09990131B2 Managing memory in a multiprocessor system 有权
公开(公告)号：US09990131B2
公开(公告)日：2018-06-05
申请号：US14493081
申请日：2014-09-22
申请人： Xilinx, Inc.
发明人： Ygal Arbel , Sagheer Ahmad , James J. Murray , Nishit Patel , Ahmad R. Ansari
IPC分类号： G06F3/06 , G06F13/16 , G06F9/30
CPC分类号： G06F3/0604 , G06F3/0655 , G06F3/0683 , G06F9/3004 , G06F13/1657 , G06F2003/0697
摘要： In an example, a circuit to manage memory between a first and second microprocessors each of which is coupled to a control circuit, includes: first and second memory circuits; and a switch circuit coupled to the first and second memory circuits, and memory interfaces of the first and second microprocessors, the switch circuit having a mode signal as input. The switch is configured to selectively operate in one of a first mode or a second mode based on the mode signal such that, in the first mode, the switch circuit couples the first memory circuit to the memory interface of the first microprocessor and the second memory circuit to the memory interface of the second microprocessor and, in the second mode, the switch circuit selectively couples the first or second memory circuits to the memory interface of either the first or second microprocessor.

27. 发明授权

US09772897B1 Methods and systems for improving safety of processor system 有权
公开(公告)号：US09772897B1
公开(公告)日：2017-09-26
申请号：US14576771
申请日：2014-12-19
申请人： Xilinx, Inc.
发明人： Sagheer Ahmad , Giulio Corradi
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/16
摘要： A processing subsystem for providing diagnostic of a processing system is provided. The processing subsystem includes a real-time processing unit that receives a first input that includes data from one or more sensors and processes the first input to generate first output that controls an actuator. The processing subsystem also includes a power and safety management unit that receives a second input and processes the second input to generate second output for testing of the first output. A method and a system for providing diagnostic for a processing system are provided as well.

28. 发明授权

US09720868B2 Bridging inter-bus communications 有权
公开(公告)号：US09720868B2
公开(公告)日：2017-08-01
申请号：US14325238
申请日：2014-07-07
申请人： Xilinx, Inc.
发明人： Ygal Arbel , Sagheer Ahmad , Sarosh I. Azad
IPC分类号： G06F13/364 , G06F13/40 , G06F12/14 , G06F21/78 , G06F21/85
CPC分类号： G06F13/404 , G06F12/1441 , G06F12/145 , G06F21/78 , G06F21/85
摘要： Approaches for bridging communication between first and second buses are disclosed. Address translation information and associated security indicators are stored in a memory. Each access request from the first bus includes a first requester security indicator and a requested address. Each access request from the first bus and directed to the second bus is either rejected, or translated and communicated to the second bus, based on the requester security indicator and the security indicator associated with the address translation information for the requested address. Each access request from the second bus to the first bus includes the requested address, and the access request is translated and communicated to the first bus along with the security indicator that is associated with the address translation information for the requested address.

29. 发明授权

US09696789B2 Sub-system power management control 有权
公开(公告)号：US09696789B2
公开(公告)日：2017-07-04
申请号：US14462492
申请日：2014-08-18
申请人： Xilinx, Inc.
发明人： Sagheer Ahmad , Ahmad R. Ansari , Soren Brinkmann
IPC分类号： G06F1/32 , G06F13/24
CPC分类号： G06F1/3287 , G06F1/3215 , G06F12/1009 , G06F12/1027 , G06F13/24 , Y02D10/13 , Y02D10/14 , Y02D10/171
摘要： An apparatus is disclosed that includes a processing sub-system having a plurality of processor circuits and an interrupt control circuit. The interrupt control circuit is configured to, in response to a peripheral interrupt, initiate performance of a task indicated by the peripheral interrupt by at least one of the plurality of processor circuits. The processing sub-system is configured to generate a power-down control signal in response to suspension of the plurality of processor circuits. A power management circuit disables power to the processing sub-system, including the interrupt control circuit, in response to the power-down control signal. The power management circuit enables power to the processing sub-system in response to a power-up control signal. The apparatus also includes a proxy interrupt control circuit configured to generate the power-up control signal in response to receiving a peripheral interrupt and power to the processing sub-system being disabled.

30. 发明授权

US09529686B1 Error protection for bus interconnect circuits 有权
标题翻译：总线互连电路的错误保护
公开(公告)号：US09529686B1
公开(公告)日：2016-12-27
申请号：US14527469
申请日：2014-10-29
申请人： Xilinx, Inc.
发明人： Ygal Arbel , Sagheer Ahmad
IPC分类号： G01R31/28 , G06F11/00 , G06F11/30
CPC分类号： G06F11/3027 , G06F11/00
摘要： In an approach for detecting faults on a bus interconnect that connects a bus master circuit to bus slave circuits, application program code and fault detection program code are concurrently executed by a bus master circuit. The application program code initiates first bus transactions to the bus slave circuits, and the fault detection program code initiates second bus transactions to the bus slave circuits for detection of faults in data channels of the bus interconnect. An error code generator circuit generates error codes from addresses of the first and second bus transactions. The error codes are transmitted with the first and second bus transactions on address channels of the bus interconnect to addressed ones of the bus slave circuits. Respective error code checker circuits coupled between the bus interconnect and the bus slave circuits determine whether or not the addresses of the bus transactions are correct based on the error codes.
摘要翻译：在用于检测将总线主机电路连接到总线从电路的总线互连上的故障的方法中，应用程序代码和故障检测程序代码由总线主机电路同时执行。应用程序代码向总线从属电路发起第一总线事务，并且故障检测程序代码向总线从电路发起第二总线事务，以检测总线互连的数据通道中的故障。错误代码生成器电路从第一和第二总线事务的地址生成错误代码。总线互连的地址信道上的第一和第二总线事务发送到寻址的总线从属电路的错误代码。耦合在总线互连和总线从属电路之间的各个错误代码校验器电路基于错误代码确定总线事务的地址是否正确。

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