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21. 发明授权

US07844871B2 Test interface for memory elements 失效
标题翻译：测试界面的内存元素
公开(公告)号：US07844871B2
公开(公告)日：2010-11-30
申请号：US12268903
申请日：2008-11-11
申请人： Uwe Brandt , Stefan Buettner , Werner Juchmes , Juergen Pille
发明人： Uwe Brandt , Stefan Buettner , Werner Juchmes , Juergen Pille
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C29/32 , G11C2029/3202
摘要： A method for testing memory elements of an integrated circuit with an array built in self test (ABIST) comprises providing an ABIST interface to interface between an ABIST engine and a plurality of latches of a memory element under test, providing a multiplex (MUX) stage adjacent a scan input port of each latch, providing functional signal inputs to a data input port of the latches, setting the latches to an ABIST mode by activating an ABIST enable signal and delivering the ABIST enable signal to each of the latches, generating a plurality of ABIST test signals with the ABIST engine, applying the ABIST test signals in parallel to the scan input ports of the latches, determining whether one or more test patterns have been executed, and setting the latches to a normal run mode by deactivating the ABIST enable signal.
摘要翻译：一种用于测试具有内置于自检（ABIST）中的阵列的集成电路的存储器元件的方法，包括提供ABIST接口以在ABIST引擎和被测存储元件的多个锁存器之间进行接口，提供多路复用（MUX）级邻近每个锁存器的扫描输入端口，向锁存器的数据输入端口提供功能信号输入，通过激活ABIST使能信号并将ABIST使能信号传送到每个锁存器，将锁存器设置为ABIST模式，产生多个的ABIST测试信号与ABIST引擎并行地应用ABIST测试信号并且与锁存器的扫描输入端口并行，确定是否执行了一个或多个测试模式，并通过停用ABIST使能来将锁存器设置为正常运行模式信号。

22. 发明申请

US20100122128A1 TEST INTERFACE FOR MEMORY ELEMENTS 失效
标题翻译：记忆元素的测试界面
公开(公告)号：US20100122128A1
公开(公告)日：2010-05-13
申请号：US12268903
申请日：2008-11-11
申请人： Uwe Brandt , Stefan Buettner , Werner Juchmes , Juergen Pille
发明人： Uwe Brandt , Stefan Buettner , Werner Juchmes , Juergen Pille
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/16 , G11C29/32 , G11C2029/3202
摘要： A method for testing memory elements of an integrated circuit with an array built in self test (ABIST) comprises providing an ABIST interface to interface between an ABIST engine and a plurality of latches of a memory element under test, providing a multiplex (MUX) stage adjacent a scan input port of each latch, providing functional signal inputs to a data input port of the latches, setting the latches to an ABIST mode by activating an ABIST enable signal and delivering the ABIST enable signal to each of the latches, generating a plurality of ABIST test signals with the ABIST engine, applying the ABIST test signals in parallel to the scan input ports of the latches, determining whether one or more test patterns have been executed, and setting the latches to a normal run mode by deactivating the ABIST enable signal.
摘要翻译：一种用于测试具有内置于自检（ABIST）中的阵列的集成电路的存储器元件的方法，包括提供ABIST接口以在ABIST引擎和被测存储元件的多个锁存器之间进行接口，提供多路复用（MUX）级邻近每个锁存器的扫描输入端口，向锁存器的数据输入端口提供功能信号输入，通过激活ABIST使能信号并将ABIST使能信号传送到每个锁存器，将锁存器设置为ABIST模式，产生多个的ABIST测试信号与ABIST引擎并行地应用ABIST测试信号并且与锁存器的扫描输入端口并行，确定是否执行了一个或多个测试模式，并通过停用ABIST使能来将锁存器设置为正常运行模式信号。

23. 发明申请

US20070189061A1 Asymmetrical Random Access Memory Cell, Memory Comprising Asymmetrical Memory Cells And Method To Operate Such A Memory 失效
标题翻译：非对称随机存取存储器单元，包含非对称存储单元的存储器和操作这样的存储器的方法
公开(公告)号：US20070189061A1
公开(公告)日：2007-08-16
申请号：US11669369
申请日：2007-01-31
申请人： Stefan Buettner , Torsten Mahnke , Wolfgang Penth , Otto Wagner
发明人： Stefan Buettner , Torsten Mahnke , Wolfgang Penth , Otto Wagner
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： Asymmetrical random access memory cell, memory comprising asymmetrical memory cells and method to operate such a memory The invention relates to an asymmetrical random access memory cell (1) comprising cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (b1t, b1c) of a pair of complementary bit-lines, which are connected via a pass-transistors (21, 31), wherein said cross coupled inverters (2, 3) have different switching thresholds and exhibit asymmetrical physical behaviours, wherein an additional pass-transistor (4) is provided in series to one of the pass-transistors (21) between one of the nodes (22) and its dedicated bit-line (blc). Further the invention relates to a random access memory comprising such memory cells and to a method of operating such a memory.
摘要翻译：不对称随机存取存储器单元，包括不对称存储器单元的存储器和用于操作这种存储器的方法本发明涉及一种非对称随机存取存储单元（1），包括交叉耦合的反相器（2,3），它们在其节点（22,32））通过一对互补位线的分开的位线（b 1 t，b 1 c），其经由传输晶体管（21,31）连接，其中所述交叉耦合的反相器（2,3）具有不同的切换阈值并表现出不对称的物理行为，其中附加的传输晶体管（4）与节点（22）中的一个与其专用位线（blc）之间的一个传输晶体管（21）串联提供。此外，本发明涉及包括这种存储器单元的随机存取存储器以及操作这种存储器的方法。

24. 发明授权

US5764587A Static wordline redundancy memory device 失效
标题翻译：静态字线冗余存储设备
公开(公告)号：US5764587A
公开(公告)日：1998-06-09
申请号：US765987
申请日：1997-01-10
申请人： Stefan Buettner , Jurgen Pille , Dieter Wendel , Friedrich Christian Wernicke
发明人： Stefan Buettner , Jurgen Pille , Dieter Wendel , Friedrich Christian Wernicke
IPC分类号： G11C11/413 , G06F11/20 , G06F12/16 , G11C8/00 , G11C29/00 , G11C29/04
CPC分类号： G11C29/78 , G11C29/848
摘要： The invention relates to a memory device comprising a set of word decoders W, a set of wordline drivers WL, a plurality of switches S to connect a subset of the wordline drivers to the set of word decoders and storage means 5 for the storage of information indicative of a defective wordline. The wordline drivers include a predefined subset of wordline drivers which are to be used when none of the wordlines are defective and a plurality of second subsets of wordline drivers which are to be used when one of the wordlines is defective. The memory device further includes logic means 4 for logically and permanently assigning one of the subsets to the set of word decoders in response to the information stored in the storage means, by controlling the switches S to connect one of the second subsets of wordline drivers to the set of word decoders.
摘要翻译： PCT No.PCT / EP95 / 02183 Sec。 371日期1997年1月10日 102（e）日期1997年1月10日PCT归档1995年6月7日PCT公布。公开号WO96 / 41264 日期：1996年12月19日本发明涉及包括一组字解码器W，一组字线驱动器WL，多个开关S以将字线驱动器的子集连接到一组字解码器和存储装置5的存储器件用于存储指示有缺陷的字线的信息。字线驱动器包括字线驱动器的预定义子集，当字线不是有缺陷时要使用的字线驱动器的子集，以及当字线之一有缺陷时要使用的多个字线驱动器的第二子集。存储装置还包括逻辑装置4，用于通过控制开关S将字线驱动器的第二子集中的一个连接到字线驱动器的一个，将逻辑上和永久地将一个子集合分配给字解码器集合，以响应存储在存储装置中的信息一组字解码器。

25. 发明授权

US08422313B2 Reduced power consumption memory circuitry 失效
标题翻译：降低功耗记忆电路
公开(公告)号：US08422313B2
公开(公告)日：2013-04-16
申请号：US13284480
申请日：2011-10-28
申请人： Stefan Buettner , David A. Hrusecky , Werner Juchmes , Wolfgang Penth , Rolf Sautter
发明人： Stefan Buettner , David A. Hrusecky , Werner Juchmes , Wolfgang Penth , Rolf Sautter
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/18 , G11C7/12 , G11C29/846 , G11C2207/005
摘要： In a circuit that reduces power consumption in an array system of memory cells accessible in parallel, a local evaluation circuit is connected to a memory cell and a global bit line of the array system of memory cells. A selection circuitry splits the global bit line into an upper part and a lower part of the global bit line. The selection circuitry is adapted to receive an early set prediction signal and to connect the upper part of the global bit line to the lower part of the global bit line based on the early set prediction signal. The early set prediction signal indicates whether a set of memory cells, which include the memory cell, is being read. The circuit also includes a N:1 multiplexer connected to the lower part of the global bit line to receive the lower part of the global bit line as input.
摘要翻译：在可以并行访问的存储单元的阵列系统中降低功耗的电路中，本地评估电路连接到存储器单元阵列系统的存储单元和全局位线。选择电路将全局位线分割成全局位线的上部和下部。选择电路适于接收早期设定的预测信号，并且基于早期设定的预测信号将全局位线的上部连接到全局位线的下部。早期设置的预测信号指示是否正在读取包括存储器单元的一组存储单元。该电路还包括连接到全局位线的下部的N：1多路复用器，以接收全局位线的下部作为输入。

26. 发明授权

US07992475B2 Plate workpiece processing 有权
标题翻译：板材加工
公开(公告)号：US07992475B2
公开(公告)日：2011-08-09
申请号：US12428748
申请日：2009-04-23
申请人： Stefan Buettner
发明人： Stefan Buettner
IPC分类号： B26D5/00
CPC分类号： B21D28/06 , B21D28/10 , B21D35/003 , Y10T83/0457 , Y10T83/0524 , Y10T83/9428
摘要： A plate workpiece processing method includes utilizing one or more cutting devices of a machine tool to perform first and second cutting operations on a plate workpiece. During the first cutting operation, the workpiece is moved relative to cutting device(s) used for the first cutting operation, at least two cut-outs are partially formed in the workpiece with only a common residual connection left that jointly connects the partially formed cut-outs to a remaining portion of the workpiece and that is shortened along one or more cutting lines of the second cutting operation to a size that is larger than a working area of the cutting device(s) used for the second cutting operation. During the second cutting operation, the workpiece is maintained stationary supported by the machine tool, the shortened common residual connection is severed along the cutting line(s) to completely separate the cut-outs from the remaining portion of the workpiece.
摘要翻译：平板工件加工方法包括利用机床的一个或多个切割装置在平板工件上执行第一和第二切割操作。在第一切割操作期间，工件相对于用于第一切割操作的切割装置移动，至少两个切口部分地形成在工件中，仅剩下共同的剩余连接，共同连接部分形成的切口输出到工件的剩余部分，并且沿着第二切割操作的一个或多个切割线被缩短到大于用于第二切割操作的切割装置的工作区域的尺寸。在第二次切割操作期间，工件由机床保持固定，缩短的共同残留连接沿着切割线切断，以将切口与工件的其余部分完全分离。

27. 发明申请

US20100095726A1 CUTTING AND/OR FORMING PLATE WORKPIECES 有权
标题翻译：切割和/或形成板工作
公开(公告)号：US20100095726A1
公开(公告)日：2010-04-22
申请号：US12579558
申请日：2009-10-15
申请人： Stefan Buettner
发明人： Stefan Buettner
IPC分类号： B21B15/00 , G06F19/00 , B26D5/20
CPC分类号： B23D23/00 , B21D22/04 , B21D28/265 , B23D36/0008 , Y10T83/162 , Y10T83/8696
摘要： A method for processing a plate workpiece supported on a workpiece support. The method includes moving a tool die and a tool punch along a stroke axis and toward a processing position above a support plane of the workpiece support. The processing position corresponds to a region of the plate workpiece having a formed shape, which extends upwardly from the support plane of the workpiece support.
摘要翻译：一种用于加工支撑在工件支架上的板材工件的方法。该方法包括沿着行程轴线并且朝向工件支撑件的支撑平面上方的加工位置移动工具模具和工具冲头。处理位置对应于从工件支撑件的支撑平面向上延伸的具有成形形状的板状工件的区域。

28. 发明申请

US20090223334A1 Plate Workpiece Processing 有权
标题翻译：板工件加工
公开(公告)号：US20090223334A1
公开(公告)日：2009-09-10
申请号：US12428748
申请日：2009-04-23
申请人： Stefan Buettner
发明人： Stefan Buettner
IPC分类号： B26D3/00
CPC分类号： B21D28/06 , B21D28/10 , B21D35/003 , Y10T83/0457 , Y10T83/0524 , Y10T83/9428
摘要： A plate workpiece processing method for obtaining at least two workpiece cut-outs from a plate workpiece. The method includes utilizing one or more cutting devices of a machine tool to perform a first cutting operation and a second cutting operation on a plate workpiece. During the first cutting operation, with the plate workpiece moving relative to the cutting device or cutting devices used for the first cutting operation, at least two workpiece cut-outs are partially formed in the plate workpiece with only a common residual connection being left that jointly connects the partially formed workpiece cut-outs to a remaining portion of the plate workpiece and that is shortened along one or more cutting lines of the second cutting operation to a size that fits within a working area of the cutting device or cutting devices used for the second cutting operation. During the second cutting operation, with the plate workpiece being maintained stationary relative to a workpiece support of the machine tool, the shortened common residual connection is severed, via the cutting device or cutting devices used for the second cutting operation, along the one or more cutting lines of the second cutting operation to completely separate the workpiece cut-outs from the remaining portion of the plate workpiece.
摘要翻译：一种用于从板工件获得至少两个工件切口的板材加工方法。该方法包括利用机床的一个或多个切割装置在平板工件上执行第一切割操作和第二切割操作。在第一次切割操作期间，随着平板工件相对于用于第一次切割操作的切割装置或切割装置移动，至少两个工件切口部分地形成在板工件中，只剩下共同的残留连接将部分形成的工件切口连接到板工件的剩余部分，并且沿着第二切割操作的一条或多条切割线将其缩短到适合于切割装置的工作区域或用于第二次切割操作。在第二切割操作期间，相对于机床的工件支撑件，平板工件保持静止，通过切割装置或用于第二切割操作的切割装置沿着一个或多个切割部分切断缩短的共同残留连接第二切割操作的切割线将工件切口与板工件的其余部分完全分离。

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