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21. 发明申请

US20080013715A1 Cryptography processing units and multiplier 有权
标题翻译：密码处理单元和乘数
公开(公告)号：US20080013715A1
公开(公告)日：2008-01-17
申请号：US11323993
申请日：2005-12-30
申请人： Wajdi Feghali , William Hasenplaugh , Gilbert Wolrich , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Wajdi Feghali , William Hasenplaugh , Gilbert Wolrich , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
IPC分类号： H04L9/28
CPC分类号： G06F7/52 , G06F9/3001 , G06F9/3881 , G06F9/3885 , G06F21/72
摘要： In general, in one aspect, the disclosure describes a system including multiple programmable processing units, a dedicated hardware multiplier, and at least one bus connecting the multiple processing units and multiplier.
摘要翻译：通常，在一个方面，本公开描述了包括多个可编程处理单元，专用硬件乘法器和连接多个处理单元和乘法器的至少一个总线的系统。

22. 发明申请

US20070192547A1 Programmable processing unit 有权
标题翻译：可编程处理单元
公开(公告)号：US20070192547A1
公开(公告)日：2007-08-16
申请号：US11354404
申请日：2006-02-14
申请人： Wajdi Feghali , William Hasenplaugh , Gilbert Wolrich , Daniel Cutter , Vinodh Gopal
发明人： Wajdi Feghali , William Hasenplaugh , Gilbert Wolrich , Daniel Cutter , Vinodh Gopal
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F9/30145 , G06F7/5324 , G06F9/3001 , G06F9/30014 , G06F9/30036 , G06F9/3004 , G06F9/383 , G06F21/602 , G06F21/72
摘要： In general, in one aspect, the disclosure describes a processing unit that includes an input buffer to store data received by the processing unit, a memory, an arithmetic logic unit coupled to the input buffer and to the memory, an output buffer; and control logic having access to a control store of program instructions, the control logic to process instructions including an instruction to transfer data from the input buffer to the memory and an instruction to cause the arithmetic logic unit to perform an operation on operands provided by at least one of the memory and the input buffer, the instruction to output results of the operation to at least one of the memory and the output buffer.
摘要翻译：通常，在一个方面，本发明描述了一种处理单元，其包括用于存储由处理单元接收的数据的输入缓冲器，存储器，耦合到输入缓冲器和存储器的算术逻辑单元，输出缓冲器; 以及具有访问程序指令的控制存储的控制逻辑，所述控制逻辑用于处理包括将数据从所述输入缓冲器传送到所述存储器的指令的指令，以及使所述算术逻辑单元对由所述输入缓冲器提供的操作数执行操作的指令至少一个存储器和输入缓冲器，将操作结果输出到至少一个存储器和输出缓冲器的指令。

23. 发明申请

US20160191238A1 SMS4 ACCELERATION HARDWARE 有权
标题翻译： SMS4加速硬件
公开(公告)号：US20160191238A1
公开(公告)日：2016-06-30
申请号：US14582707
申请日：2014-12-24
申请人： Kirk YAP , Gilbert Wolrich , Sudhir Satpathy , Sean Gulley , Vinodh Gopal , Sanu Mathew , Wajdi Feghali
发明人： Kirk YAP , Gilbert Wolrich , Sudhir Satpathy , Sean Gulley , Vinodh Gopal , Sanu Mathew , Wajdi Feghali
IPC分类号： H04L9/08
CPC分类号： H04L9/0822 , G09C1/00 , H04L9/0631 , H04L2209/122
摘要： Embodiments of an invention for SMS4 acceleration hardware are disclosed. In an embodiment, an apparatus includes SMS4 hardware and key transformation hardware. The SMS4 hardware is to execute a round of encryption and a round of key expansion. The key transformation hardware is to transform a key to provide for the SMS4 hardware to execute a round of decryption.
摘要翻译：公开了用于SMS4加速硬件的发明的实施例。在一个实施例中，一种装置包括SMS4硬件和密钥变换硬件。 SMS4硬件是执行一轮加密和一轮关键扩展。密钥转换硬件是转换密钥以提供SMS4硬件来执行一轮解密。

24. 发明申请

US20100141488A1 ACCELERATED DECOMPRESSION 有权
标题翻译：加速解散
公开(公告)号：US20100141488A1
公开(公告)日：2010-06-10
申请号：US12332083
申请日：2008-12-10
申请人： Selcuk Baktir , Vinodh Gopal , Gilbert Wolrich , Prashant Paliwal , Wajdi Feghali
发明人： Selcuk Baktir , Vinodh Gopal , Gilbert Wolrich , Prashant Paliwal , Wajdi Feghali
IPC分类号： H03M7/40
CPC分类号： H03M7/40 , H03M7/425
摘要： Techniques for decompressing a compressed input by determining, according to an ordering of allowable codewords, an offset for a variable length codeword detected in the input; accessing a record at the determined offset in a data structure having one record for each of the allowable codewords, each record including a portion for at least one of a literal value and a length value and a portion for a type value indicative of whether the record is for a literal or a length; and determining a decompressed output based at least in part on the accessed record.
摘要翻译：用于通过根据允许的码字的排序确定在输入中检测到的可变长度码字的偏移来解压缩压缩输入的技术; 在具有每个可允许代码字的一个记录的数据结构中以确定的偏移量访问记录，每个记录包括用于文字值和长度值中的至少一个的部分，以及指示记录的类型值的部分是一个字面或长度; 以及至少部分地基于所访问的记录来确定解压缩的输出。

25. 发明申请

US20070174372A1 Programmable processing unit having multiple scopes 失效
标题翻译：具有多个示波器的可编程处理单元
公开(公告)号：US20070174372A1
公开(公告)日：2007-07-26
申请号：US11354670
申请日：2006-02-14
申请人： Wajdi Feghali , William Hasenplaugh , Gilbert Wolrich , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Wajdi Feghali , William Hasenplaugh , Gilbert Wolrich , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
IPC分类号： G06F15/00
CPC分类号： G06F21/602
摘要： In general, in one aspect, the disclosure describes a processing unit that includes a memory, an arithmetic logic unit, and control logic having access to program instructions of a control store. The control logic includes logic to access multiple sets of variables, variables in the different sets of variables being identically referenced by instructions, associate a one of the sets of variables as the current set of variables to be used in instructions that are executed by the arithmetic logic unit, change the set of variables associated with the current set of variables in response to a procedure call or exit, and alter the value of a variable of a set of the variables other than the set of variables associated with the current set of variables in response to an instruction.
摘要翻译：通常，在一个方面，本公开描述了一种处理单元，其包括存储器，算术逻辑单元和具有访问控制存储器的程序指令的控制逻辑。控制逻辑包括访问多组变量的逻辑，不同变量集合中的变量由指令相同地引用，将变量集合中的一个与当前由算术执行的指令中使用的变量集合相关联逻辑单元，响应于过程调用或退出而改变与当前变量集相关联的变量集合，并且改变一组变量的值，而不是与当前变量集合相关联的变量集合响应一个指令。

26. 发明申请

US20070157030A1 Cryptographic system component 审中-公开
标题翻译：密码系统组件
公开(公告)号：US20070157030A1
公开(公告)日：2007-07-05
申请号：US11323329
申请日：2005-12-30
申请人： Wajdi Feghali , William Hasenplaugh , Gilbert Wolrich , Daniel Cutter , Vinodh Gopal
发明人： Wajdi Feghali , William Hasenplaugh , Gilbert Wolrich , Daniel Cutter , Vinodh Gopal
IPC分类号： G06F12/14
CPC分类号： G06F21/602
摘要： In general, in aspect, the disclosure describes a system integrated on a single die that includes a first processor core to receive commands from at least one other processor core to perform at least one specified transformative operation on specified data, multiple processing units to perform transformative operations on data, a shared memory, and logic to transfer data between a one of the set of multiple processing units and the shared memory.
摘要翻译：一般来说，在本发明中，本公开描述了集成在单个管芯上的系统，其包括第一处理器核心，用于接收来自至少一个其他处理器核心的命令以对指定数据执行至少一个指定的变换操作，多个处理单元执行变换对数据的操作，共享存储器和用于在多个处理单元组中的一个处理单元和共享存储器之间传送数据的逻辑。

27. 发明授权

US07607068B2 Apparatus and method for generating a Galois-field syndrome 失效
标题翻译：用于产生伽罗瓦氏综合征的装置和方法
公开(公告)号：US07607068B2
公开(公告)日：2009-10-20
申请号：US11469222
申请日：2006-08-31
申请人： Vinodh Gopal , Gilbert M. Wolrich , Daniel Cutter , Wajdi Feghali , Robert P. Ottavi
发明人： Vinodh Gopal , Gilbert M. Wolrich , Daniel Cutter , Wajdi Feghali , Robert P. Ottavi
IPC分类号： G11C29/00
CPC分类号： G06F11/1076 , G06F2211/1054 , G06F2211/1057
摘要： The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most significant bit (MSB) of the first data byte and a Galois-field polynomial to generate a first intermediate output; XORing each bit of the first intermediate output with the least significant bits (LSBs) of the first data byte to generate a second intermediate output; MUXing the second intermediate output with each bit of the first data byte to generate a third intermediate output; XORing each bit of the third intermediate output with each bit of the second data byte to generate at a fourth intermediate output; and generating a RAID Q syndrome based on, at least in part, the fourth intermediate output. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于产生伽罗瓦域综合征的装置和方法。一个示例性方法可以包括将第一数据字节从第一存储设备加载到第一寄存器，并将第二数据字节从第二存储设备加载到第二寄存器; 将第一数据字节的最高有效位（MSB）和伽罗瓦域多项式进行比较以产生第一中间输出; 用第一数据字节的最低有效位（LSB）对第一中间输出的每个位进行异或，以产生第二中间输出; 将第二中间输出与第一数据字节的每个位进行多路复用以产生第三中间输出; 将第三中间输出的每个位与第二数据字节的每个位进行异或，以在第四中间输出处产生; 以及至少部分地基于第四中间输出产生RAID Q综合征。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

28. 发明申请

US20080059865A1 APPARATUS AND METHOD FOR GENERATING A GALOIS-FIELD SYNDROME 失效
标题翻译：用于产生GALOIS-FIELD SYNDROME的装置和方法
公开(公告)号：US20080059865A1
公开(公告)日：2008-03-06
申请号：US11469222
申请日：2006-08-31
申请人： Vinodh Gopal , Gilbert M. Wolrich , Daniel Cutter , Wajdi Feghali , Robert P. Ottavi
发明人： Vinodh Gopal , Gilbert M. Wolrich , Daniel Cutter , Wajdi Feghali , Robert P. Ottavi
IPC分类号： G11C29/00
CPC分类号： G06F11/1076 , G06F2211/1054 , G06F2211/1057
摘要： The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most significant bit (MSB) of the first data byte and a Galois-field polynomial to generate a first intermediate output; XORing each bit of the first intermediate output with the least significant bits (LSBs) of the first data byte to generate a second intermediate output; MUXing the second intermediate output with each bit of the first data byte to generate a third intermediate output; XORing each bit of the third intermediate output with each bit of the second data byte to generate at a fourth intermediate output; and generating a RAID Q syndrome based on, at least in part, the fourth intermediate output. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于产生伽罗瓦域综合征的装置和方法。一个示例性方法可以包括将第一数据字节从第一存储设备加载到第一寄存器，并将第二数据字节从第二存储设备加载到第二寄存器; 将第一数据字节的最高有效位（MSB）和伽罗瓦域多项式进行比较以产生第一中间输出; 用第一数据字节的最低有效位（LSB）对第一中间输出的每个位进行异或，以产生第二中间输出; 将第二中间输出与第一数据字节的每个位进行多路复用以产生第三中间输出; 将第三中间输出的每个位与第二数据字节的每个位进行异或，以在第四中间输出处产生; 以及至少部分地基于第四中间输出产生RAID Q综合征。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

29. 发明申请

US20080162806A1 Storage Accelerator 有权
标题翻译：存储加速器
公开(公告)号：US20080162806A1
公开(公告)日：2008-07-03
申请号：US11617966
申请日：2006-12-29
申请人： Vinodh Gopal , Yogesh Bansal , Gilbert M. Wolrich , Wajdi Feghali , Kirk Yap
发明人： Vinodh Gopal , Yogesh Bansal , Gilbert M. Wolrich , Wajdi Feghali , Kirk Yap
IPC分类号： G06F12/06
CPC分类号： G06F11/1076 , G06F2211/1057
摘要： The present disclosure provides a method for generating RAID syndromes. In one embodiment the method may include loading a first data byte of a first disk block and a first data byte of a second disk block from a storage device to an arithmetic logic unit. The method may further include XORing the first data byte of the first disk block and the first data byte of the second disk block to generate a first result and storing the first result in a results buffer. The method may also include iteratively repeating, loading intermediate data bytes corresponding to the first disk block and intermediate data bytes corresponding to the second disk block from the storage device to the arithmetic logic unit. The method may additionally include XORing the intermediate data bytes corresponding to the first disk block and the intermediate data bytes corresponding to the second disk block to generate intermediate results and generating a RAID syndrome based on, at least in part, the intermediate results. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于生成RAID综合征的方法。在一个实施例中，该方法可以包括将第一磁盘块的第一数据字节和第二磁盘块的第一数据字节从存储设备加载到算术逻辑单元。该方法还可以包括将第一磁盘块的第一数据字节和第二磁盘块的第一数据字节进行异或，以产生第一结果并将第一结果存储在结果缓冲器中。该方法还可以包括将对应于第一磁盘块的中间数据字节和对应于第二磁盘块的中间数据字节从存储设备反复重复加载到算术逻辑单元。该方法还可以包括对与第一磁盘块相对应的中间数据字节和对应于第二磁盘块的中间数据字节进行异或，以产生中间结果，并至少部分地基于中间结果生成RAID综合征。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

30. 发明申请

US20190045031A1 LOW-LATENCY LINK COMPRESSION SCHEMES 审中-公开
公开(公告)号：US20190045031A1
公开(公告)日：2019-02-07
申请号：US16014690
申请日：2018-06-21
申请人： Wajdi Feghali , Vinodh Gopal , Kirk Yap , Sean Gulley , Simon Peffers
发明人： Wajdi Feghali , Vinodh Gopal , Kirk Yap , Sean Gulley , Simon Peffers
IPC分类号： H04L29/06 , H04L12/863
摘要： Methods and apparatus for low-latency link compression schemes. Under the schemes, selected packets or messages are dynamically selected for compression in view of current transmit queue levels. The latency incurred during compression and decompression is not added to the data-path, but sits on the side of the transmit queue. The system monitors the queue depth and, accordingly, initiates compression jobs based on the depth. Different compression levels may be dynamically selected and used based on queue depth. Under various schemes, either packets or messages are enqueued in the transmit queue or pointers to such packets and messages are enqueued. Additionally, packets/message may be compressed prior to being enqueued, or after being enqueued, wherein an original uncompressed packet is replaced with a compressed packet. Compressed and uncompressed packets may be stored in queues or buffers and transmitted using a different numbers of transmit cycles based on their compression ratios. The schemes may be implemented to improve the effective bandwidth of various types of links, including serial links, bus-type links, and socket-to-socket links in multi-socket systems.

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