专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US08271570B2 Unified integer/galois field (2m) multiplier architecture for elliptic-curve crytpography 有权
标题翻译：用于椭圆曲线凝固图的统一整数/伽罗瓦域（2m）乘法器结构
公开(公告)号：US08271570B2
公开(公告)日：2012-09-18
申请号：US11772166
申请日：2007-06-30
申请人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali
发明人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali
IPC分类号： G06F7/00
CPC分类号： G06F7/72 , G06F7/5324 , G06F7/725 , G06F2207/382
摘要： A unified integer/Galois-Field 2m multiplier performs multiply operations for public-key systems such as Rivert, Shamir, Aldeman (RSA), Diffie-Hellman key exchange (DH) and Elliptic Curve Cryptosystem (ECC). The multiply operations may be performed on prime fields and different composite binary fields in independent multipliers in an interleaved fashion.
摘要翻译：统一的整数/伽罗瓦域2m乘法器为诸如Rivert，Shamir，Aldeman（RSA），Diffie-Hellman密钥交换（DH）和椭圆曲线加密系统（ECC）的公钥系统执行乘法运算。可以以交错方式在独立乘法器中的主场和不同的复合二进制字段上执行乘法运算。

22. 发明申请

US20090006512A1 NORMAL-BASIS TO CANONICAL-BASIS TRANSFORMATION FOR BINARY GALOIS-FIELDS GF(2m) 有权
标题翻译：二维GALOIS-FIEL的经典基础变换的正态关系GF（2m）
公开(公告)号：US20090006512A1
公开(公告)日：2009-01-01
申请号：US11772176
申请日：2007-06-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
IPC分类号： G06F7/00 , G06F15/00
CPC分类号： G06F7/724
摘要： Basis conversion from normal form to canonical form is provided for both generic polynomials and special irreducible polynomials in the form of “all ones”, referred to as “all-ones-polynomials” (AOP). Generation and storing of large matrices is minimized by creating matrices on the fly, or by providing an alternate means of computing a result with minimal hardware extensions.
摘要翻译：为“通用多项式”（AOP）的“全部”形式的通用多项式和特殊不可约数多项式提供从正常形式到规范形式的基础转换。通过在飞行中创建矩阵，或者通过提供以最小的硬件扩展来计算结果的替代方法来最小化大矩阵的生成和存储。

23. 发明申请

US20090003594A1 MODULUS SCALING FOR ELLIPTIC-CURVE CRYPTOGRAPHY 有权
标题翻译：用于ELLIPTIC-CURVE CRYPTOGRAPHY的MODULUS SCALING
公开(公告)号：US20090003594A1
公开(公告)日：2009-01-01
申请号：US11772165
申请日：2007-06-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
IPC分类号： H04L9/30 , G06F7/72
CPC分类号： G06F7/72 , G06F5/01 , G06F7/723 , G06F7/725 , H04L9/3066
摘要： Modulus scaling applied a reduction techniques decreases time to perform modular arithmetic operations by avoiding shifting and multiplication operations. Modulus scaling may be applied to both integer and binary fields and the scaling multiplier factor is chosen based on a selected reduction technique for the modular arithmetic operation.
摘要翻译：使用缩减技术的模量缩放通过避免移位和乘法运算来减少执行模数运算的时间。可以将模量缩放应用于整数和二进制字段，并且基于用于模数运算的选定的缩减技术来选择缩放倍数因子。

24. 发明申请

US20090003593A1 UNIFIED SYSTEM ARCHITECTURE FOR ELLIPTIC-CURVE CRYTPOGRAPHY 有权
标题翻译：用于ELLIPTIC-CURVE CRYTPOGRAPHY的统一系统架构
公开(公告)号：US20090003593A1
公开(公告)日：2009-01-01
申请号：US11772163
申请日：2007-06-30
申请人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali
发明人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali
IPC分类号： H04L9/30 , G06F7/72
CPC分类号： H04L9/3066 , G06F7/5324 , G06F7/725
摘要： A system for performing public key encryption is provided. The system supports mathematical operations for a plurality of public key encryption algorithms such as Rivert, Shamir, Aldeman (RSA) and Diffie-Hellman key exchange (DH) and Elliptic Curve Cryptosystem (ECC). The system supports both prime fields and different composite binary fields.
摘要翻译：提供了一种执行公钥加密的系统。该系统支持诸如Rivert，Shamir，Aldeman（RSA）和Diffie-Hellman密钥交换（DH）和椭圆曲线加密系统（ECC）的多个公共密钥加密算法的数学运算。系统支持主域和不同的复合二进制域。

25. 发明申请

US20080147768A1 Configurable Exponent Fifo 有权
标题翻译：可配置指数
公开(公告)号：US20080147768A1
公开(公告)日：2008-06-19
申请号：US11610841
申请日：2006-12-14
申请人： Vinodh Gopal , Wajdi Feghali , Gilbert Wolrich , Daniel Cutter , Robert P. Ottavi
发明人： Vinodh Gopal , Wajdi Feghali , Gilbert Wolrich , Daniel Cutter , Robert P. Ottavi
IPC分类号： G06F7/38
CPC分类号： G06F7/723
摘要： The present disclosure provides a system and method for performing modular exponentiation. The method includes loading a first word of a vector from memory into a first register and subsequently loading the first word from the first register to a second register. The method may also include loading a second word into the first register and loading at least one bit from the second register into an arithmetic logic unit. The method may further include performing modular exponentiation on the at least one bit to generate a result and generating a public key based upon, at least in part, the result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于执行模幂运算的系统和方法。该方法包括将来自存储器的向量的第一字加载到第一寄存器中，并随后将第一个字从第一寄存器加载到第二寄存器。该方法还可以包括将第二字加载到第一寄存器中并将至少一个比特从第二寄存器加载到算术逻辑单元中。该方法还可以包括在至少一个比特上执行模幂运算以产生结果，并且至少部分地基于结果生成公开密钥。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

26. 发明授权

US07539718B2 Method and apparatus for performing Montgomery multiplications 失效
标题翻译：执行蒙哥马利乘法的方法和装置
公开(公告)号：US07539718B2
公开(公告)日：2009-05-26
申请号：US10944354
申请日：2004-09-16
申请人： Kamal J. Koshy , Gilbert Wolrich , Jaroslaw J. Sydir , Wajdi K. Feghali
发明人： Kamal J. Koshy , Gilbert Wolrich , Jaroslaw J. Sydir , Wajdi K. Feghali
IPC分类号： G06F7/38
CPC分类号： G06F7/728 , G06F2207/3884
摘要： An arrangement is provided for performing Montgomery multiplications. A Montgomery multiplication comprises a plurality of iterations of basic operations (e.g., carry-save additions), and is performed by a Montgomery multiplication engine (MME). Basic operations in each iteration may be performed by multiple Montgomery multiplication processing elements (MMPEs). An MME may be arranged to pipeline the process of performing iterations of multiple basic operations and other operations required to complete a Montgomery multiplication both horizontally and vertically. An MME may also be arranged to interleave processes of performing two Montgomery multiplications.
摘要翻译：提供了执行蒙哥马利乘法的安排。蒙哥马利乘法包括多个基本操作的迭代（例如，进位保存添加），并且由蒙哥马利乘法引擎（MME）执行。每个迭代中的基本操作可以由多个蒙哥马利乘法处理元件（MMPE）执行。 MME可以被布置成管理执行多个基本操作的迭代的过程以及完成水平和垂直的蒙哥马利乘法所需的其他操作。还可以将MME布置成交织执行两个蒙哥马利乘法的处理。

27. 发明授权

US07373514B2 High-performance hashing system 有权
标题翻译：高性能散列系统
公开(公告)号：US07373514B2
公开(公告)日：2008-05-13
申请号：US10624533
申请日：2003-07-23
申请人： Jon H. Krueger , Wajdi K. Feghali , Gilbert Wolrich
发明人： Jon H. Krueger , Wajdi K. Feghali , Gilbert Wolrich
IPC分类号： H04L9/00
CPC分类号： G06F17/30949 , G06F17/10
摘要： A high-performance, low-latency data retrieval system is disclosed using hash functions. Given a set of input data, the data retrieval system may generate one or more index values and a signature value according to a predetermined hash function. The index values may be applied to respective data arrays to access a data unit therein. The data unit may include signatures previously developed when populating the array. If a signature from the data unit matches the signature generated from the hash function, then the associated index may be applied to a second portion of the respective data array to retrieve requested data.
摘要翻译：公开了使用散列函数的高性能，低延迟数据检索系统。给定一组输入数据，数据检索系统可以根据预定的散列函数生成一个或多个索引值和签名值。可以将索引值应用于相应的数据阵列以访问其中的数据单元。数据单元可以包括当填充阵列时先前开发的签名。如果来自数据单元的签名与从哈希函数产生的签名相匹配，则相关联的索引可以被应用于相应数据阵列的第二部分以检索所请求的数据。

28. 发明申请

US20140095845A1 APPARATUS AND METHOD FOR EFFICIENTLY EXECUTING BOOLEAN FUNCTIONS 审中-公开
标题翻译：有效执行布尔函数的装置和方法
公开(公告)号：US20140095845A1
公开(公告)日：2014-04-03
申请号：US13631807
申请日：2012-09-28
申请人： Vinodh Gopal , Wajdi Feghali , Gilbert Wolrich , Kirk Yap
发明人： Vinodh Gopal , Wajdi Feghali , Gilbert Wolrich , Kirk Yap
IPC分类号： G06F9/30
摘要： An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, a processor according to one embodiment of the invention comprises: a set of registers for storing packed operands; Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the three source operands, wherein the Boolean operation comprises: combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value; reading the bit from the identified bit position of the immediate value; and storing the bit from the identified bit position of the immediate value in a destination register.
摘要翻译：描述了一种用于在流水线处理器中执行有效的布尔运算的装置和方法，其在一个实施例中不本地支持三个操作数指令。例如，根据本发明的一个实施例的处理器包括：一组用于存储打包操作数的寄存器; 用于执行单个指令的布尔运算逻辑，其使用打包在该组寄存器中的三个或更多个源操作数，布尔运算逻辑读取至少三个源操作数，并且立即值对三个源操作数执行布尔运算，其中，布尔操作包括：组合从三个操作数中的每一个读取的位以形成立即值的索引，该索引标识立即值内的位位置; 从识别的位置读取该位从立即值; 并将来自所识别的立即值的比特位置的比特存储在目的地寄存器中。

29. 发明申请

US20100153829A1 RESIDUE GENERATION 失效
标题翻译：残留生成
公开(公告)号：US20100153829A1
公开(公告)日：2010-06-17
申请号：US12336029
申请日：2008-12-16
申请人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi Feghali
发明人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi Feghali
IPC分类号： H03M13/09 , G06F7/72 , G06F11/10
CPC分类号： G06F7/724 , H03M13/091
摘要： In one embodiment, circuitry is provided to generate a residue based at least in part upon operations and a data stream generated based at least in part upon a packet. The operations may include at least one iteration of at least one reduction operation including (a) multiplying a first value with at least one portion of the data stream, and (b) producing a reduction by adding at least one other portion of the data stream to a result of the multiplying. The operations may include at least one other reduction operation including (c) producing another result by multiplying with a second value at least one portion of another stream based at least in part upon the reduction, (d) producing a third value by adding at least one other portion of the another stream to the another result, and (e) producing the residue by performing a Barrett reduction based at least in part upon the third value.
摘要翻译：在一个实施例中，提供电路以至少部分地基于至少部分地基于分组产生的操作和数据流来生成残差。操作可以包括至少一个缩减操作的迭代，包括（a）将第一值与数据流的至少一部分相乘，以及（b）通过添加数据流的至少一个其他部分来产生减少是乘法的结果。所述操作可以包括至少一个其它减少操作，其包括（c）至少部分地基于所述减少，通过与另一个流的至少一部分乘以第二值来产生另一结果，（d）通过至少加入来产生第三值另一个流的另一部分到另一个结果，以及（e）至少部分地基于第三个值执行巴雷特还原来产生残留物。

30. 发明授权

US08189792B2 Method and apparatus for performing cryptographic operations 有权
标题翻译：用于执行加密操作的方法和装置
公开(公告)号：US08189792B2
公开(公告)日：2012-05-29
申请号：US12005680
申请日：2007-12-28
申请人： Brent Boswell , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Vinodh Gopal , Srinivas Chennupaty , Makaram Raghunandan
发明人： Brent Boswell , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Vinodh Gopal , Srinivas Chennupaty , Makaram Raghunandan
IPC分类号： G06F21/00
CPC分类号： H04L9/0631 , H04L2209/125
摘要： In one embodiment, the present invention includes a processor having logic to perform a round of a cryptographic algorithm responsive to first and second round micro-operations to perform the round on first and second pairs of columns, where the logic includes dual datapaths that are half the width of the cryptographic algorithm width (or smaller). Additional logic may be used to combine the results of the first and second round micro-operations to obtain a round result. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括处理器，其具有响应于第一和第二轮微操作执行一轮加密算法以在第一和第二列列上执行循环的逻辑，其中该逻辑包括半数的双数据通路加密算法宽度（或更小）的宽度。可以使用附加逻辑来组合第一和第二轮微操作的结果以获得圆形结果。描述和要求保护其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式