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21. 发明授权

US07358555B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07358555B2
公开(公告)日：2008-04-15
申请号：US11409040
申请日：2006-04-24
申请人： Toshiaki Iwamatsu , Takashi Ipposhi , Tatsuhiko Ikeda , Shigeto Maegawa
发明人： Toshiaki Iwamatsu , Takashi Ipposhi , Tatsuhiko Ikeda , Shigeto Maegawa
IPC分类号： H01L27/108
CPC分类号： H01L27/0811 , H01L27/1203
摘要： While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered.Decoupling capacitors DM1 and DM2 are connected between the source line connected to the pad for high-speed circuits which supplies electric power to circuit block C1, and the ground line connected to a ground pad, and the capacitor array for high-speed circuits is formed. A plurality of decoupling capacitor DM1 are connected between the source line connected to the pad for low-speed circuits which supplies electric power to circuit block C2, and the ground line connected to a ground pad, and the capacitor array for low-speed circuits is formed. Decoupling capacitor DM1 differs in the dimension of a gate electrode from DM2.
摘要翻译：在提高去耦电容器的频率特性的同时，抑制源极线路的电压降并使其稳定，从而提供抑制去耦电容器布置的面积效率下降的半导体器件。去耦电容器DM1和DM2连接在连接到用于为电路块C 1供电的高速电路的焊盘的源极线和连接到接地焊盘的地线之间，并且用于高速的电容器阵列形成电路。多个去耦电容器DM1连接在连接到用于向电路块C 2供电的低速电路的焊盘的源极线和连接到接地焊盘的地线之间，以及用于低速的电容器阵列形成电路。去耦电容器DM 1的栅电极尺寸与DM2不同。

22. 发明授权

US07321152B2 Thin-film transistor and method of fabricating the same 失效
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US07321152B2
公开(公告)日：2008-01-22
申请号：US11498800
申请日：2006-08-04
申请人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
发明人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
IPC分类号： H01L29/76 , H01L31/113
CPC分类号： H01L29/78609 , H01L27/124 , H01L29/41733 , H01L29/458 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78639
摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same.A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
摘要翻译：提供了通过将具有不同导电类型的多晶硅层彼此连接而形成的薄膜晶体管，其防止由杂质扩散引起的不便的发生及其制造方法。漏极（6），沟道（7）和源极（8）通过多晶硅一体地形成在第二氧化膜（4）的表面上。漏极（6）形成为通过形成为到达焊盘层（3）的上表面的接触孔（5）与焊盘层（3）（第二多晶半导体层）连接。定位在接触孔（5）（开口）的底部的衬垫层（3）设置有硼注入区域BR。

23. 发明申请

US20060237726A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060237726A1
公开(公告)日：2006-10-26
申请号：US11409040
申请日：2006-04-24
申请人： Toshiaki Iwamatsu , Takashi Ipposhi , Tatsuhiko Ikeda , Shigeto Maegawa
发明人： Toshiaki Iwamatsu , Takashi Ipposhi , Tatsuhiko Ikeda , Shigeto Maegawa
IPC分类号： H01L29/04
CPC分类号： H01L27/0811 , H01L27/1203
摘要： While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered. Decoupling capacitors DM1 and DM2 are connected between the source line connected to the pad for high-speed circuits which supplies electric power to circuit block C1, and the ground line connected to a ground pad, and the capacitor array for high-speed circuits is formed. A plurality of decoupling capacitor DM1 are connected between the source line connected to the pad for low-speed circuits which supplies electric power to circuit block C2, and the ground line connected to a ground pad, and the capacitor array for low-speed circuits is formed. Decoupling capacitor DM1 differs in the dimension of a gate electrode from DM2.
摘要翻译：在提高去耦电容器的频率特性的同时，抑制源极线路的电压降并使其稳定，从而提供抑制去耦电容器布置的面积效率下降的半导体器件。去耦电容器DM1和DM2连接在连接到用于为电路块C 1供电的高速电路的焊盘的源极线和连接到接地焊盘的地线之间，并且用于高速的电容器阵列形成电路。多个去耦电容器DM1连接在连接到用于向电路块C 2供电的低速电路的焊盘的源极线和连接到接地焊盘的地线之间，以及用于低速的电容器阵列形成电路。去耦电容器DM 1的栅电极尺寸与DM2不同。

24. 发明申请

US20060043494A1 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060043494A1
公开(公告)日：2006-03-02
申请号：US11210666
申请日：2005-08-25
申请人： Takashi Ipposhi , Toshiaki Iwamatsu , Shigeto Maegawa
发明人： Takashi Ipposhi , Toshiaki Iwamatsu , Shigeto Maegawa
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , H01L21/84
摘要： A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a P+ region with a high impurity concentration thereat. The surface of a body contact is provide with a barrier metal. A silicide is formed between the body contact and the SOI layer as a result of the reaction of the barrier metal and the SOI layer.
摘要翻译：在SOI层和触点之间的连接处（即，在元件隔离绝缘膜下）形成肖特基结，而不形成具有高杂质浓度的P + +区域。身体接触的表面提供阻挡金属。作为阻挡金属和SOI层的反应的结果，在本体接触和SOI层之间形成硅化物。

25. 发明授权

US07541644B2 Semiconductor device with effective heat-radiation 有权
标题翻译：具有有效散热的半导体器件
公开(公告)号：US07541644B2
公开(公告)日：2009-06-02
申请号：US10793841
申请日：2004-03-08
申请人： Yuuichi Hirano , Shigenobu Maeda , Takuji Matsumoto , Takashi Ipposhi , Shigeto Maegawa
发明人： Yuuichi Hirano , Shigenobu Maeda , Takuji Matsumoto , Takashi Ipposhi , Shigeto Maegawa
IPC分类号： H01L29/72
CPC分类号： H01L23/481 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/1203 , H01L29/78639 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device has a silicon layer (SOI layer) (12) formed through a silicon oxide film (11) on a support substrate (10). A transistor (T1) is formed in the SOI layer (12). The wiring (17a) is connected with a source of the transistor (T1) through a contact plug (15a). A back metal (18) is formed on an under surface (back surface) of the support substrate (10) and said back metal (18) is connected with the wiring (17a) through a heat radiating plug (16). The contact plug (15a), the heat radiating plug (16) the wiring (17a) and the back metal (18) is made of a metal such as aluminum, tungsten and so on which has a higher thermal conductivity than that of the silicon oxide film (11) and the support substrate (10).
摘要翻译：半导体器件具有通过支撑衬底（10）上的氧化硅膜（11）形成的硅层（SOI层）（12）。在SOI层（12）中形成晶体管（T1）。布线（17a）通过接触插塞（15a）与晶体管（T1）的源极连接。背衬金属（18）形成在支撑基板（10）的下表面（背面）上，背面金属（18）通过散热塞（16）与布线17a连接。接触插头（15a），散热塞（16），布线（17a）和背金属（18）由诸如铝，钨等的金属制成，其具有比硅的热导率更高的导热性氧化膜（11）和支撑基板（10）。

26. 发明申请

US20070007595A1 Semiconductor device with effective heat-radiation 审中-公开
标题翻译：具有有效散热的半导体器件
公开(公告)号：US20070007595A1
公开(公告)日：2007-01-11
申请号：US11520640
申请日：2006-09-14
申请人： Yuuichi Hirano , Shigenobu Maeda , Takuji Matsumoto , Takashi Ipposhi , Shigeto Maegawa
发明人： Yuuichi Hirano , Shigenobu Maeda , Takuji Matsumoto , Takashi Ipposhi , Shigeto Maegawa
IPC分类号： H01L27/12
CPC分类号： H01L23/481 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/1203 , H01L29/78639 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device has a silicon layer (SOI layer) (12) formed through a silicon oxide film (11) on a support substrate (10). A transistor (T1) is formed in the SOI layer (12). The wiring (17a) is connected with a source of the transistor (T1) through a contact plug (15a). A back metal (18) is formed on an under surface (back surface) of the support substrate (10) and said back metal (18) is connected with the wiring (17a) through a heat radiating plug (16). The contact plug (15a), the heat radiating plug (16) the wiring (17a) and the back metal (18) is made of a metal such as aluminum, tungsten and so on which has a higher thermal conductivity than that of the silicon oxide film (11) and the support substrate (10).
摘要翻译：半导体器件具有通过支撑衬底（10）上的氧化硅膜（11）形成的硅层（SOI层）（12）。在SOI层（12）中形成晶体管（T 1）。布线（17a）通过接触插塞（15A）与晶体管（T 1）的源极连接。背衬金属（18）形成在支撑基板（10）的下表面（背面）上，所述背金属（18）通过散热塞（16）与布线（17a）连接。接触塞（15A），散热塞（16），布线（17a）和背金属（18）由诸如铝，钨等的金属制成，其具有比氧化硅膜（11）和支撑基板（10）。

27. 发明授权

US06310377B1 Semiconductor device having an SOI structure 失效
标题翻译：具有SOI结构的半导体器件
公开(公告)号：US06310377B1
公开(公告)日：2001-10-30
申请号：US09134896
申请日：1998-08-17
申请人： Shigenobu Maeda , Yasuo Yamaguchi , Il Jung Kim , Yasuo Inoue , Shigeto Maegawa , Takashi Ipposhi
发明人： Shigenobu Maeda , Yasuo Yamaguchi , Il Jung Kim , Yasuo Inoue , Shigeto Maegawa , Takashi Ipposhi
IPC分类号： H01L2701
CPC分类号： H01L21/76202 , H01L21/76264 , H01L21/76281 , H01L21/76291 , H01L27/11807 , H01L27/1203
摘要： FS-isolated fields (10a, 10b). LOCOS-isolated fields (11c, 11d). FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can he provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.
摘要翻译： FS隔离场（10a，10b）。 LOCOS隔离场（11c，11d）。 FS隔离场（10e，10f），LOCOS隔离场（11g，11h）和FS隔离场（10i）按此顺序排列。因此，可以提供主布局，其中将具有被提供固定电位的主体和具有不具有固定电位的主体的SOI晶体管混合。

28. 发明授权

US5808341A Semiconductor device having an SOI structure 失效
标题翻译：具有SOI结构的半导体器件
公开(公告)号：US5808341A
公开(公告)日：1998-09-15
申请号：US747933
申请日：1996-11-12
申请人： Shigenobu Maeda , Yasuo Yamaguchi , Il Jung Kim , Yasuo Inoue , Shigeto Maegawa , Takashi Ipposhi
发明人： Shigenobu Maeda , Yasuo Yamaguchi , Il Jung Kim , Yasuo Inoue , Shigeto Maegawa , Takashi Ipposhi
IPC分类号： H01L21/762 , H01L21/82 , H01L27/118 , H01L27/12 , H01L29/786 , H01L29/00
CPC分类号： H01L21/76202 , H01L21/76264 , H01L27/11807 , H01L27/1203 , H01L21/76281 , H01L21/76291
摘要： FS-isolated fields (10a, 10b), LOCOS-isolated fields (11c, 11d), FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can be provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.
摘要翻译： FS隔离场（10a，10b），LOCOS隔离场（11c，11d），FS隔离场（10e，10f），LOCOS隔离场（11g，11h）和FS隔离场（10i）这个命令。因此，可以提供主布局，其中将具有被提供固定电位的体的SOI晶体管和具有不具有固定电位的体的SOI晶体管混合。

29. 发明授权

US07494883B2 Semiconductor device having a trench isolation and method of fabricating the same 失效
标题翻译：具有沟槽隔离的半导体器件及其制造方法
公开(公告)号：US07494883B2
公开(公告)日：2009-02-24
申请号：US11543213
申请日：2006-10-05
申请人： Toshiaki Iwamatsu , Takashi Ipposhi , Takuji Matsumoto , Shigenobu Maeda
发明人： Toshiaki Iwamatsu , Takashi Ipposhi , Takuji Matsumoto , Shigenobu Maeda
IPC分类号： H01L21/336
CPC分类号： H01L21/2652 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.
摘要翻译：本发明提供一种制造半导体器件的方法，其中通过防止在有源区中形成沟道阻挡注入层来防止晶体管特性的劣化。形成抗蚀剂掩模，以便在形成PMOS晶体管的区域上具有开口。通过离子通过部分隔离氧化膜的能量进行沟道停止注入，在SOI层中产生杂质分布的峰，从而在部分隔离氧化膜的SOI层内形成沟道停止层，即，隔离区域。这里要植入的杂质是N型杂质。在使用磷的情况下，其注入能量设定为例如60〜120keV，通道阻挡层的密度为1×10 17〜1×10 19 / cm 3。此时，沟道停止注入的杂质在与有源区对应的SOI层中不停止。

30. 发明授权

US07067881B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07067881B2
公开(公告)日：2006-06-27
申请号：US10754539
申请日：2004-01-12
申请人： Takuji Matsumoto , Takashi Ipposhi , Toshiaki Iwamatsu , Yuuichi Hirano
发明人： Takuji Matsumoto , Takashi Ipposhi , Toshiaki Iwamatsu , Yuuichi Hirano
IPC分类号： H01L27/01
CPC分类号： H01L29/66545 , H01L21/28052 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/41766 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7834 , H01L29/7845
摘要： A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer (3) that are located between the bottoms of element isolation insulating films (5) and the top surface of a BOX layer (2), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions (11) are formed to reach the upper surface of the BOX layer (2), the junction capacitance of source/drain regions (12) is not increased.
摘要翻译：提供一种半导体器件及其制造方法，其可以适当地避免隔离击穿电压的降低，而不会引起诸如结电容增加的不利影响。在通过形成凹部（14）使硅层（3）变薄之后形成杂质导入区域（11）。因此，在位于元件隔离绝缘膜（5）的底部和BOX层（2）的顶面之间的p型硅层（3）的部分中不会注入n型杂质，避免了还原的隔离击穿电压。此外，由于杂质引入区域（11）形成为到达BOX层（2）的上表面，所以源极/漏极区域（12）的结电容不增加。

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