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21. 发明申请

US20120144161A1 CARRYLESS MULTIPLICATION PREFORMATTING APPARATUS AND METHOD 有权
标题翻译：无轴承多重预制装置和方法
公开(公告)号：US20120144161A1
公开(公告)日：2012-06-07
申请号：US12960246
申请日：2010-12-03
申请人： Timothy A. Elliott
发明人： Timothy A. Elliott
IPC分类号： G06F15/76 , G06F7/52
CPC分类号： G06F7/5338
摘要： An apparatus is provided for performing carryless multiplication. The apparatus has an opcode dectector and a carryless preformat unit. The opcode dectector is configured to receive a carryless multiplication instruction, and is configured to assert a carryless signal responsive to receipt of the carryless multiplication instruction. The carryless preformat unit is configured to partition the first operand into parts responsive to assertion of the carryless signal, where the parts are configured such that a Booth encoder selects first partial products corresponding to a second operand and is precluded from selection of second partial products corresponding to the second operand, and where the second partial products are results of implicit carry operations. The first partial products are exclusive-ORed together to yield a carryless multiplication result.
摘要翻译：提供一种用于执行无载乘法的装置。该设备具有操作码检测器和无卡纸预格式单元。操作码检测器被配置为接收无轮乘法指令，并且被配置为响应于无载乘法指令的接收来断言无卡信号。无轮胎预定位单元被配置为响应于无卡信号的断言而将第一操作数分成部分，其中部件被配置为使得布斯编码器选择对应于第二操作数的第一部分乘积，并且不排除相应的第二部分乘积的选择到第二个操作数，第二个部分产品是隐含进位操作的结果。第一部分产品被排列在一起以产生无载乘法结果。

22. 发明申请

US20120143933A1 CARRYLESS MULTIPLICATION UNIT 有权
标题翻译：无关多路复用单元
公开(公告)号：US20120143933A1
公开(公告)日：2012-06-07
申请号：US12960231
申请日：2010-12-03
申请人： Timothy A. Elliott
发明人： Timothy A. Elliott
IPC分类号： G06F7/523
CPC分类号： G06F7/5338
摘要： An apparatus having a carryless preformat unit, a Booth encoder, a compressor, a left shifter, and exclusive-OR logic. The carryless preformat unit receives a multiplier operand and partitions the multiplier operand into parts. The Booth encoder receives the parts and directs selection of first partial products of a multiplicand that do not reflect implicit carry operations. The compressor sums the first partial products via a configuration of carry save adders that generate sum bits and carry bits, where generation of the carry bits is disabled during execution of the carryless multiplication. The left shifter shifts bits of one or more outputs of the compressor. The exclusive-OR logic is coupled to the compressor and the left shifter, and is configured to execute an exclusive-OR function on the outputs to yield a carryless multiplication result.
摘要翻译：一种具有无载体预格式化单元，布斯编码器，压缩器，左移位器和异或逻辑的装置。无卡格式的格式化单元接收乘法器操作数，并将乘法器操作数分成多个部分。展位编码器接收零件并指示不反映隐式进位操作的被乘数的第一部分乘积的选择。压缩器经由生成和位和进位位的进位保存加法器的配置来合成第一部分乘积，其中在执行无载乘法期间禁止进位位的生成。左移位器移位压缩器的一个或多个输出的位。异或逻辑耦合到压缩器和左移位器，并且被配置为对输出执行异或运算以产生无载乘法结果。

23. 发明授权

US5583805A Floating-point processor having post-writeback spill stage 失效
标题翻译：浮点处理器具有回写后溢出阶段
公开(公告)号：US5583805A
公开(公告)日：1996-12-10
申请号：US352661
申请日：1994-12-09
申请人： Timothy A. Elliott , Robert T. Golla , Christopher H. Olson , Terence M. Potter
发明人： Timothy A. Elliott , Robert T. Golla , Christopher H. Olson , Terence M. Potter
IPC分类号： G06F7/57 , G06F7/38
CPC分类号： G06F7/483 , G06F7/49915
摘要： An apparatus for handling special cases outside of normal floating-point arithmetic functions is provided that is used in a floating-point unit used for calculating arithmetic functions. The floating-point unit generates an exponent portion and a mantissa portion and a writeback stage is coupled to the exponent portion and to the mantissa portion and is specifically used to handle the special cases outside the normal float arithmetic functions. A spill stage is also provided and is coupled to the writeback stage to receive a resultant exponent and mantissa. A register file unit is coupled to the writeback stage and the spill stage through a plurality of rename busses, which are used to carry results between the writeback stage and spill stage and the register file. The spill stage is serially coupled to the writeback stage so as to provide a smooth operation in the transition of operating on the results from the writeback stage for the exponent and mantissa. Each rename bus has a pair of tri-state buffers, one used to couple the rename bus to the writeback stage and the other used to couple the rename bus to the spill stage. The instruction dispatcher also provides location information for directing the results from the writeback stage and the spill stage before the result is completed.
摘要翻译：提供了用于处理正常浮点运算功能之外的特殊情况的装置，用于计算算术功能的浮点单元。浮点单元产生指数部分和尾数部分，并且回写阶段耦合到指数部分和尾数部分，并且专门用于处理普通浮点运算功能之外的特殊情况。还提供溢出阶段并且耦合到回写阶段以接收所得到的指数和尾数。寄存器文件单元通过多个重命名总线耦合到回写阶段和溢出阶段，这些总线用于在回写阶段和溢出阶段之间携带结果和寄存器文件。溢出级串联耦合到回写阶段，以便在针对指数和尾数的回写阶段的结果的转换中提供平滑的操作。每个重命名总线都有一对三态缓冲器，一个用于将重命名总线耦合到回写阶段，另一个用于将重命名总线耦合到溢出级。指令调度器还提供位置信息，用于在结果完成之前从写回阶段和溢出阶段引导结果。

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