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21. 发明授权

US08364989B2 Power supply input selection circuit 有权
标题翻译：电源输入选择电路
公开(公告)号：US08364989B2
公开(公告)日：2013-01-29
申请号：US11861843
申请日：2007-09-26
申请人： Bernd Zimek , Josef Haid , Thomas Leutgeb , Thomas Baglin , Walter Kargl
发明人： Bernd Zimek , Josef Haid , Thomas Leutgeb , Thomas Baglin , Walter Kargl
IPC分类号： G06F1/00 , G06F9/00 , G06F9/24 , G06F15/177
CPC分类号： H02M1/10
摘要： A power supply input selection circuit for selecting one of a plurality of power supply inputs to supply power to a driven circuit. The power supply input selection circuit includes a power supply input switching circuit configured to provide operating power to the driven circuit by routing a selected one of the power supply inputs to the driven circuit as a function of power supply selection information; and a logic circuit configured to change the power supply selection information if a default power mode does not match a desired power mode, the logic circuit being further configured to reset the power supply input selection circuit after changing the power supply selection information, the power supply selection information being maintained during the reset, in which the power supply input switching circuit selects a desired one of the power supply inputs after the logic circuit resets the power supply input selection circuit.
摘要翻译：一种电源输入选择电路，用于选择多个电源输入中的一个以向驱动电路供电。电源输入选择电路包括：电源输入切换电路，被配置为根据电源选择信息将所选择的一个电源输入路由到驱动电路，向驱动电路提供工作电源; 以及逻辑电路，其被配置为如果默认功率模式与期望的功率模式不匹配则改变所述电源选择信息，所述逻辑电路还被配置为在改变所述电源选择信息之后复位所述电源输入选择电路，所述电源在复位期间保持选择信息，其中电源输入切换电路在逻辑电路复位电源输入选择电路之后选择所需的一个电源输入。

22. 发明授权

US07830719B2 Power dependent memory access 有权
标题翻译：电源相关内存访问
公开(公告)号：US07830719B2
公开(公告)日：2010-11-09
申请号：US12034864
申请日：2008-02-21
申请人： Thomas Leutgeb , Josef Haid , Stefan Rueping
发明人： Thomas Leutgeb , Josef Haid , Stefan Rueping
IPC分类号： C16
CPC分类号： G11C7/1006 , G11C5/142 , G11C7/1045 , G11C7/22
摘要： An apparatus and method of accessing a memory by determining available power, and accessing a number of bits of the memory in parallel, wherein the number of bits accessed in parallel is based at least in part on the available power.
摘要翻译：一种通过确定可用功率并且并行访问存储器的多个位来访问存储器的装置和方法，其中并行访问的位数目至少部分地基于可用功率。

23. 发明授权

US07772909B2 Supplying power to, and clocking, clocked loads 有权
标题翻译：为时钟负载供电和计时
公开(公告)号：US07772909B2
公开(公告)日：2010-08-10
申请号：US11944833
申请日：2007-11-26
申请人： Josef Haid , Walter Kargl , Thomas Leutgeb
发明人： Josef Haid , Walter Kargl , Thomas Leutgeb
IPC分类号： G06F1/04 , G06F1/00
CPC分类号： G06F1/305 , G06K19/0723
摘要： A supply power can be fed in at a circuit arrangement for supplying power to, and clocking, clocked loads. The circuit arrangement provides a clock signal at a frequency and a supply voltage, the frequency and/or the supply voltage being able to be controlled by the circuit arrangement in such a manner that a power tapped off at the output and the supply power fed in are in a predefined relationship.
摘要翻译：可以以电路布置馈送电源，以向定时负载供电和计时。电路装置以频率和电源电压提供时钟信号，频率和/或电源电压能够由电路装置控制，使得在输出端分接电源和供电电源处于预定的关系。

24. 发明申请

US20080170458A1 APPARATUS AND METHOD FOR REDUCING LEAKAGE CURRENTS OF INTEGRATED CIRCUITS HAVING AT LEAST ONE TRANSISTOR 失效
标题翻译：用于降低最小一个晶体管的集成电路泄漏电流的装置和方法
公开(公告)号：US20080170458A1
公开(公告)日：2008-07-17
申请号：US11668214
申请日：2007-01-29
申请人： Josef Haid , Thomas Kuenemund , Thomas Leutgeb , Bernd Zimek
发明人： Josef Haid , Thomas Kuenemund , Thomas Leutgeb , Bernd Zimek
IPC分类号： G05F1/10
CPC分类号： G11C5/14
摘要： An apparatus for reducing leakage currents of an integrated circuit having at least one transistor, wherein the at least one transistor is connected between a supply potential and a first reference potential, the apparatus including a controller for controlling the first reference potential in dependence on the supply potential.
摘要翻译：一种用于减少具有至少一个晶体管的集成电路的泄漏电流的装置，其中所述至少一个晶体管连接在电源电势和第一参考电位之间，所述装置包括用于根据供电来控制第一参考电位的控制器潜在。

25. 发明申请

US20080026712A1 EDGE EVALUATION OF ASK-MODULATED SIGNALS 有权
标题翻译： ASK调制信号的边缘评估
公开(公告)号：US20080026712A1
公开(公告)日：2008-01-31
申请号：US11548844
申请日：2006-10-12
申请人： Thomas Leutgeb , Helmut Koroschetz , Walter Kargl
发明人： Thomas Leutgeb , Helmut Koroschetz , Walter Kargl
IPC分类号： G06F3/033
CPC分类号： H04L27/06 , H04L25/061
摘要： Signal processing circuit including a demodulator that receives a receive signal with signal edges, and outputs a demodulated receive signal with transitions from a first level to a second level or vice versa at signal edges of the receive signal, wherein points of time of the transitions depend on the steepnesses of the signal edges. The circuit also includes an edge evaluator that receives the receive signal, and outputs an evaluation signal which includes information about the steepnesses of the signal edges. The circuit also includes a signal generator that receives the output of the demodulator, receives the output of the edge evaluator, and outputs a corrected demodulated receive signal with transitions whose points of time are set with regard to the points of time of the transitions of the demodulated receive signal based on the evaluation signal in order to reduce influences of different steepnesses of the signal edges.
摘要翻译：信号处理电路包括解调器，其接收具有信号边缘的接收信号，并且在接收信号的信号边缘处输出具有从第一电平到第二电平或反之亦然的解调接收信号，其中转变点的时间点依赖在信号边缘的陡度上。电路还包括接收接收信号的边缘评估器，并且输出包括关于信号边缘的陡度的信息的评估信号。电路还包括一个信号发生器，它接收解调器的输出，接收边缘评估器的输出，并输出一个经过修正的解调接收信号，该转换的时间点设置为相对于基于评估信号的解调接收信号，以减少信号边缘的不同陡度的影响。

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