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21. 发明申请

US20090102015A1 Integrated Circuit, Memory Cell Array, Memory Cell, Memory Module, Method of Operating an Integrated Circuit, and Method of Manufacturing an Integrated Circuit 审中-公开
标题翻译：集成电路，存储单元阵列，存储单元，存储器模块，操作集成电路的方法以及制造集成电路的方法
公开(公告)号：US20090102015A1
公开(公告)日：2009-04-23
申请号：US11874113
申请日：2007-10-17
申请人： Ulrich Klostermann , Dietmar Gogl
发明人： Ulrich Klostermann , Dietmar Gogl
IPC分类号： H01L29/92 , H01L21/77
CPC分类号： H01L45/1233 , H01L27/222 , H01L27/2436 , H01L27/2463 , H01L45/085
摘要： According to one embodiment of the present invention, an integrated circuit includes a plurality of resistivity changing memory cells, each memory cell including a top electrode, a bottom electrode and resistivity changing material being disposed between the top electrode and the bottom electrode. The top electrodes together form a continuous common first electrode. Alternatively, a first continuous common electrode which is electrically connected to all top electrodes is disposed above the top electrodes. A second electrode connectable to a fixed potential is disposed above the first electrode such that the first electrode and the second electrode together form a capacitor.
摘要翻译：根据本发明的一个实施例，集成电路包括多个电阻率变化存储单元，每个存储单元包括设置在顶电极和底电极之间的顶电极，底电极和电阻率变化材料。顶部电极一起形成连续的公共第一电极。或者，电连接到所有顶部电极的第一连续公共电极设置在顶部电极的上方。可连接到固定电位的第二电极设置在第一电极上方，使得第一电极和第二电极一起形成电容器。

22. 发明授权

US07411854B2 System and method for controlling constant power dissipation 有权
标题翻译：用于控制恒定功耗的系统和方法
公开(公告)号：US07411854B2
公开(公告)日：2008-08-12
申请号：US11406073
申请日：2006-04-18
申请人： Ulrich Klostermann , Dietmar Gogl
发明人： Ulrich Klostermann , Dietmar Gogl
IPC分类号： G11C5/14
CPC分类号： G11C11/16 , G11C5/14 , G11C11/2297 , G11C13/0038
摘要： A method for controlling the constant power dissipation of a memory cell includes initially measuring the resistance of the memory cell, and subsequently controlling a source to apply a variable level of current or voltage to the memory cell. The variable level of the applied current or voltage is determined in proportion to the measured resistance of the memory cell so as to result in a predefined level of power dissipation within the memory cell, said dissipated power operable to heat the memory cell.
摘要翻译：用于控制存储单元的恒定功耗的方法包括：初始测量存储单元的电阻，并随后控制一个源，以将可变电平的电流或电压施加到存储单元。所施加的电流或电压的可变电平根据所测量的存储单元的电阻成比例地确定，从而导致存储单元内的预定功率耗散水平，所述耗散功率可操作以加热存储单元。

23. 发明授权

US07391639B2 Memory device and method for reading data 有权
标题翻译：用于读取数据的存储器件和方法
公开(公告)号：US07391639B2
公开(公告)日：2008-06-24
申请号：US11354281
申请日：2006-02-14
申请人： Dietmar Gogl
发明人： Dietmar Gogl
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C7/12 , G11C13/0026 , G11C13/004 , G11C13/04 , G11C2013/0042 , G11C2213/79
摘要： A memory with memory cells, wherein a memory cell includes a resistive element and a switch, wherein the memory cells are connected with a common plate line and with respective bit lines, wherein the common plate line supplies a plate voltage, wherein the switches include control inputs that are connected with word lines for controlling the switching states, wherein the word lines are connected with a word line driver that supplies selected word lines with a voltage, wherein the bit lines are connected with second switches, wherein the first bit lines are connectable by respective second switches with a first voltage level and the second bit lines are connectable by respective second switches with a second voltage level, wherein a first and a second bit line are connectable as a bit line pair with a sense amplifier, wherein the sense amplifier amplifies a voltage difference between the first and the second bit line of the bit line pair, wherein the resistive element is able to change the resistance depending on an electrical voltage that is applied across the resistive element, and wherein the second voltage level is between the plate voltage level and the first voltage level.
摘要翻译：一种具有存储器单元的存储器，其中存储单元包括电阻元件和开关，其中所述存储器单元与公共板线和各自的位线连接，其中所述公共板线提供板电压，其中所述开关包括控制与用于控制切换状态的字线连接的输入，其中字线与提供所选字线的字线驱动器连接，其中位线与第二开关连接，其中第一位线是可连接的通过具有第一电压电平的相应的第二开关，并且第二位线可由具有第二电压电平的相应的第二开关连接，其中第一和第二位线可与读出放大器作为位线对连接，其中读出放大器放大位线对的第一位线和第二位线之间的电压差，其中电阻元件能够改变t 其电阻取决于施加在电阻元件两端的电压，并且其中第二电压电平在板电压电平和第一电压电平之间。

24. 发明申请

US20080080232A1 Active write current adjustment for magneto-resistive random access memory 审中-公开
标题翻译：用于磁阻随机存取存储器的有效写入电流调整
公开(公告)号：US20080080232A1
公开(公告)日：2008-04-03
申请号：US11529569
申请日：2006-09-28
申请人： Andre Sturm , Hans-Heinrich Viehmann , Dietmar Gogl
发明人： Andre Sturm , Hans-Heinrich Viehmann , Dietmar Gogl
IPC分类号： G11C11/00 , G11C11/14 , G11C11/15
CPC分类号： G11C11/16
摘要： In a method of programming a magneto resistive memory cell, a first magnetic field is applied to the magneto resistive memory cell. It is determined whether the magneto resistive memory cell meets a programming criterion. In case that the magneto resistive memory cell does not meet the programming criterion, a second magnetic field, which is higher or lower than the first magnetic field, is applied to the magneto resistive memory cell. It is then determined whether the magneto resistive memory cell meets a programming criterion. The magnetic field is increased or decreased in case that the magneto resistive memory cell does not meet the programming criterion until the magneto resistive memory cell meets the programming criterion.
摘要翻译：在编写磁阻存储器单元的方法中，第一磁场被施加到磁阻存储器单元。确定磁阻存储器单元是否满足编程标准。在磁阻存储器单元不满足编程标准的情况下，将高于或低于第一磁场的第二磁场施加到磁阻存储器单元。然后确定磁阻存储器单元是否满足编程标准。在磁阻存储器单元不满足编程标准直到磁阻存储器单元满足编程标准的情况下，磁场增加或减小。

25. 发明申请

US20070242549A1 System and method for controlling constant power dissipation 有权
标题翻译：用于控制恒定功耗的系统和方法
公开(公告)号：US20070242549A1
公开(公告)日：2007-10-18
申请号：US11406073
申请日：2006-04-18
申请人： Ulrich Klostermann , Dietmar Gogl
发明人： Ulrich Klostermann , Dietmar Gogl
IPC分类号： G11C5/14
CPC分类号： G11C11/16 , G11C5/14 , G11C11/2297 , G11C13/0038
摘要： A method for controlling the constant power dissipation of a memory cell includes initially measuring the resistance of the memory cell, and subsequently controlling a source to apply a variable level of current or voltage to the memory cell. The variable level of the applied current or voltage is determined in proportion to the measured resistance of the memory cell so as to result in a predefined level of power dissipation within the memory cell, said dissipated power operable to heat the memory cell.
摘要翻译：用于控制存储单元的恒定功耗的方法包括：初始测量存储单元的电阻，并随后控制一个源，以将可变电平的电流或电压施加到存储单元。所施加的电流或电压的可变电平根据所测量的存储单元的电阻成比例地确定，从而导致存储单元内的预定功率耗散水平，所述耗散功率可操作以加热存储单元。

26. 发明授权

US07239537B2 Method and apparatus for current sense amplifier calibration in MRAM devices 有权
标题翻译：用于MRAM器件中电流检测放大器校准的方法和装置
公开(公告)号：US07239537B2
公开(公告)日：2007-07-03
申请号：US10905585
申请日：2005-01-12
申请人： John K. DeBrosse , Dietmar Gogl , Stefan Lammers , Hans Viehmann
发明人： John K. DeBrosse , Dietmar Gogl , Stefan Lammers , Hans Viehmann
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C29/02 , G11C29/026 , G11C29/028 , G11C2029/1204
摘要： A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel with a second load device, the second load device associated with a reference side of the sense amplifier. The first and said second plurality of trim transistors are individually activated so as to compensate for device mismatch with respect to the data and reference sides of the sense amplifier.
摘要翻译：校准磁性随机存取存储器（MRAM）电流检测放大器包括与第一负载装置并联的第一多个调整晶体管，第一负载装置与读出放大器的数据侧相关联。与第二负载装置并联地选择性地配置第二组微调晶体管，第二负载装置与感测放大器的参考侧相关联。单独激活第一和第二多个微调晶体管，以补偿相对于读出放大器的数据和参考侧的器件失配。

27. 发明申请

US20050073879A1 MRAM array having a segmented bit line 失效
标题翻译： MRAM阵列具有分段位线
公开(公告)号：US20050073879A1
公开(公告)日：2005-04-07
申请号：US10679160
申请日：2003-10-03
申请人： Dietmar Gogl , John DeBrosse
发明人： Dietmar Gogl , John DeBrosse
IPC分类号： G11C11/15 , G11C11/00
CPC分类号： G11C7/18 , G11C11/15
摘要： A magneto-resistive random access memory (MRAM) array comprises global bit lines segmented using a plurality of local bit lines. A read/write controller is connected to the switches. Switches couple the global bit line to the local bit lines. The MRAM array has low leakage currents and facilitates a high signal-to-noise (S/N) ratio of read and write operations.
摘要翻译：磁阻随机存取存储器（MRAM）阵列包括使用多个局部位线分割的全局位线。读/写控制器连接到交换机。开关将全局位线耦合到本地位线。 MRAM阵列具有低漏电流，并有助于读写操作的高信噪比（S / N）。

28. 发明申请

US20090273966A1 Integrated Circuit, Memory Cell Array, Memory Module, and Method of Operating an Integrated Circuit 有权
标题翻译：集成电路，存储单元阵列，存储器模块和操作集成电路的方法
公开(公告)号：US20090273966A1
公开(公告)日：2009-11-05
申请号：US12114466
申请日：2008-05-02
申请人： Dietmar Gogl , Rainer Leuschner , Ulrich Klostermann
发明人： Dietmar Gogl , Rainer Leuschner , Ulrich Klostermann
IPC分类号： G11C11/02
CPC分类号： G11C11/1675 , G11C11/1659
摘要： According to one embodiment of the present invention, an integrated circuit includes a plurality of thermal selectable memory cells, each memory cell being connected to a conductive line, the conductive line having a first portion for applying a heating current, and a second portion for applying a programming current. The integrated circuit is configured such that the heating current and the programming current can be routed respectively to the first and the second portion of the conductive line independently from each other.
摘要翻译：根据本发明的一个实施例，集成电路包括多个热可选择存储单元，每个存储单元连接到导电线，该导线具有用于施加加热电流的第一部分和用于施加加热电流的第二部分编程电流。集成电路被配置为使得加热电流和编程电流可以彼此独立地分别路由到导线的第一和第二部分。

29. 发明授权

US07313043B2 Magnetic Memory Array 有权
标题翻译：磁存储阵列
公开(公告)号：US07313043B2
公开(公告)日：2007-12-25
申请号：US11288494
申请日：2005-11-29
申请人： Dietmar Gogl , Daniel Braun
发明人： Dietmar Gogl , Daniel Braun
IPC分类号： G11C7/02 , G11C5/08 , G11C11/00 , G11C11/14 , G11C11/15
CPC分类号： G11C11/16 , G11C8/10
摘要： A magnetic memory is disclosed. In one embodiment, the magnetic memory array includes a plurality of cell columns and a pair of reference cell columns, including a first reference cell column and a second reference cell column. A comparator is provided with a first and a second input terminal. A switching circuit is configured to connect each of the cell columns to the first input terminal and the pair of reference cell columns coupled in parallel to the second input terminal, and configured to connect the first reference cell column to the first input terminal and the second reference cell column to the second input terminal.
摘要翻译：公开了磁存储器。在一个实施例中，磁存储阵列包括多个单元列和一对参考单元列，包括第一参考单元列和第二参考单元列。比较器具有第一和第二输入端。开关电路被配置为将每个单元列连接到与第二输入端并联耦合的第一输入端和一对参考单元列，并且被配置为将第一参考单元列连接到第一输入端，而第二参考单元列参考单元格列到第二个输入端。

30. 发明授权

US06982902B2 MRAM array having a segmented bit line 失效
标题翻译： MRAM阵列具有分段位线
公开(公告)号：US06982902B2
公开(公告)日：2006-01-03
申请号：US10679160
申请日：2003-10-03
申请人： Dietmar Gogl , John K. DeBrosse
发明人： Dietmar Gogl , John K. DeBrosse
IPC分类号： G11C11/00
CPC分类号： G11C7/18 , G11C11/15
摘要： A magneto-resistive random access memory (MRAM) array comprises global bit lines segmented using a plurality of local bit lines. A read/write controller is connected to the switches. Switches couple the global bit line to the local bit lines. The MRAM array has low leakage currents and facilitates a high signal-to-noise (S/N) ratio of read and write operations.
摘要翻译：磁阻随机存取存储器（MRAM）阵列包括使用多个局部位线分割的全局位线。读/写控制器连接到交换机。开关将全局位线耦合到局部位线。 MRAM阵列具有低漏电流，并有助于读写操作的高信噪比（S / N）。

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