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21. 发明授权

US06265895B1 Programmable logic device incorporating a memory efficient interconnection device 有权
标题翻译：可编程逻辑器件结合了高效的存储器件
公开(公告)号：US06265895B1
公开(公告)日：2001-07-24
申请号：US09525979
申请日：2000-03-15
申请人： James Schleicher , Michael J. Ferrazano
发明人： James Schleicher , Michael J. Ferrazano
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： The invention relates to an integrated circuit that incorporates a memory efficient interconnection device. Typically, the integrated circuit chip is a complex programmable logic device architecture (CPLD). By using the memory efficient interconnection device, the invention is able to reduce the quantity of memory resources required to program the interconnection device while at the same time not substantially sacrificing the probability of fitting logic functions in the CPLD. The reduction in memory resources that the CPLD must provide leads to increased availability of precious die area for other components of the CPLD.
摘要翻译：本发明涉及一种集成有记忆有效互连装置的集成电路。通常，集成电路芯片是复杂的可编程逻辑器件架构（CPLD）。通过使用存储器有效的互连装置，本发明能够减少对互连装置编程所需的存储器资源的数量，同时基本上不牺牲在CPLD中拟合逻辑功能的概率。 CPLD必须提供的内存资源的减少可以提高CPLD其他组件的可用性。

22. 发明授权

US06057707A Programmable logic device incorporating a memory efficient interconnection device 失效
标题翻译：可编程逻辑器件结合了高效的存储器件
公开(公告)号：US06057707A
公开(公告)日：2000-05-02
申请号：US16209
申请日：1998-01-30
申请人： James Schleicher , Michael J. Ferrazano
发明人： James Schleicher , Michael J. Ferrazano
IPC分类号： H03K19/177 , H03K19/094 , H03K19/173
CPC分类号： H03K19/1776 , H03K19/17736 , H03K19/1778
摘要： The invention relates to an integrated circuit that incorporates a memory efficient interconnection device. Typically, the integrated circuit chip is a complex programmable logic device architecture (CPLD). By using the memory efficient interconnection device, the invention is able to reduce the quantity of memory resources required to program the interconnection device while at the same time not substantially sacrificing the probability of fitting logic functions in the CPLD. The reduction in memory resources that the CPLD must provide leads to increased availability of precious die area for other components of the CPLD.
摘要翻译：本发明涉及一种集成有记忆有效互连装置的集成电路。通常，集成电路芯片是复杂的可编程逻辑器件架构（CPLD）。通过使用存储器有效的互连装置，本发明能够减少对互连装置编程所需的存储器资源的数量，同时基本上不牺牲在CPLD中拟合逻辑功能的概率。 CPLD必须提供的内存资源的减少可以提高CPLD其他组件的可用性。

23. 发明申请

US20070294659A1 Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits 有权
标题翻译：生产等效现场可编程门阵列和结构化应用专用集成电路的方法
公开(公告)号：US20070294659A1
公开(公告)日：2007-12-20
申请号：US11893675
申请日：2007-08-16
申请人： James Schleicher , David Karchmer
发明人： James Schleicher , David Karchmer
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/505 , G06F2217/64
摘要： Compiler flows are provided that can produce functionally equivalent field programmable gate arrays (“FPGAs”) and structured application-specific integrated circuits (“structured ASICs”). The flows may include feeding back design transformations that are performed during either flow so that a later performance of the other flow will necessarily include the same transformations, thereby helping to ensure functional equivalence. The flows may include a comparison of intermediate results in order to prove that functional equivalence is being achieved.
摘要翻译：提供了可产生功能等同的现场可编程门阵列（“FPGA”）和结构化专用集成电路（“结构化ASIC”）的编译器流。流可以包括反馈在任一流程期间执行的设计变换，使得另一流程的稍后的性能将必然包括相同的变换，由此有助于确保功能等同性。流程可以包括中间结果的比较，以证明正在实现功能等同性。

24. 发明授权

US06989689B2 Interconnection and input/output resources for programmable logic integrated circuit devices 失效
公开(公告)号：US06989689B2
公开(公告)日：2006-01-24
申请号：US10852858
申请日：2004-05-24
申请人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
发明人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
IPC分类号： H03K19/177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

25. 发明授权

US06894533B2 Interconnection and input/output resources for programmable logic integrated circuit devices 有权
标题翻译：可编程逻辑集成电路器件的互连和输入/输出资源
公开(公告)号：US06894533B2
公开(公告)日：2005-05-17
申请号：US10458431
申请日：2003-06-09
申请人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
发明人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
IPC分类号： G06F7/50 , G06F7/506 , H03K19/173 , H03K19/177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.
摘要翻译：可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间，从区域和/或区域之间进行可编程互连。这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。例如，这种双形互连资源的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分可具有明显更快的信号速度。辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

26. 发明授权

US06366120B1 Interconnection resources for programmable logic integrated circuit devices 有权
标题翻译：可编程逻辑集成电路器件的互连资源
公开(公告)号：US06366120B1
公开(公告)日：2002-04-02
申请号：US09517146
申请日：2000-03-02
申请人： James Schleicher , James Park , Sergey Shumarayev , Bruce Pedersen , Tony Ngai , Wei-Jen Huang , Victor Maruri , Rakesh Patel
发明人： James Schleicher , James Park , Sergey Shumarayev , Bruce Pedersen , Tony Ngai , Wei-Jen Huang , Victor Maruri , Rakesh Patel
IPC分类号： H03K190177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/17792
摘要： A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.
摘要翻译：可编程逻辑器件具有许多可编程逻辑区域，以及可用于在几乎任何逻辑区域之间进行互连的相对通用的，可编程的互连资源。此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近的逻辑区域之间建立互连，而不需要使用这些互连的通用互连资源。本地互连资源通过相对直接的和因此的高速互连来支持逻辑区域的灵活聚集，优选地在逻辑区域的典型二维阵列中的水平和垂直方向。由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本无边界的。

27. 发明授权

US07839167B2 Interconnection and input/output resources for programmable logic integrated circuit devices 有权
标题翻译：可编程逻辑集成电路器件的互连和输入/输出资源
公开(公告)号：US07839167B2
公开(公告)日：2010-11-23
申请号：US12356317
申请日：2009-01-20
申请人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
发明人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.
摘要翻译：可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间，从区域和/或区域之间进行可编程互连。这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。例如，这种双形互连资源的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分可具有明显更快的信号速度。辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

28. 发明申请

US20070063732A1 Area efficient fractureable logic elements 有权
$Area efficient fractureable logic elements$
标题翻译：区域有效的可断裂逻辑元件
公开(公告)号：US20070063732A1
公开(公告)日：2007-03-22
申请号：US11234538
申请日：2005-09-22
申请人： Sinan Kaptanoglu , Bruce Pedersen , James Schleicher , Jinyong Yuan , Michael Hutton , David Lewis
发明人： Sinan Kaptanoglu , Bruce Pedersen , James Schleicher , Jinyong Yuan , Michael Hutton , David Lewis
IPC分类号： H03K19/177
CPC分类号： H03K19/1737
摘要： A fracturable logic element includes a first, second, third, and fourth two-input lookup tables (2-LUTs). Each 2-LUT includes four memory elements. Each memory element is configured to hold one data bit. The fracturable logic element also includes a set of six inputs and a control circuit configured to operate in a first mode and a second mode. When the control circuit operates in the first mode, a first combinatorial output is generated using four of the set of six inputs and the first, second, third, and fourth 2-LUTs. When the control circuit operates in the second mode, a second combinatorial output is generated using a first subset of three of the set of six inputs and the first and second 2-LUTS. Additionally, when the control circuit operates in the second mode, a third combinatorial output is generated using a second subset of three of the set of six inputs and the third and fourth 2-LUTs, the first and second subsets being non-intersecting subsets of the set of six inputs.
摘要翻译：可分解逻辑元件包括第一，第二，第三和第四双输入查找表（2-LUT）。每个2-LUT包括四个存储元件。每个存储器元件被配置为保持一个数据位。可分解逻辑元件还包括一组六个输入和被配置为在第一模式和第二模式下操作的控制电路。当控制电路在第一模式下工作时，使用六个输入和第一，第二，第三和第四2-LUT中的四个产生第一组合输出。当控制电路在第二模式下操作时，使用该组六个输入和第一和第二2-LUTS中的三个的第一子集来生成第二组合输出。另外，当控制电路在第二模式下工作时，使用六组输入和第三和第四2-LUT组中的三个的第二子集来产生第三组合输出，第一和第二子集是不相交的子集一组六个输入。

29. 发明申请

US20060225008A1 Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits 有权
标题翻译：生产等效现场可编程门阵列和结构化应用专用集成电路的方法
公开(公告)号：US20060225008A1
公开(公告)日：2006-10-05
申请号：US11097633
申请日：2005-04-01
申请人： James Schleicher , David Karchmer
发明人： James Schleicher , David Karchmer
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/505 , G06F2217/64
摘要： Compiler flows are provided that can produce functionally equivalent field programmable gate arrays (“FPGAs”) and structured application-specific integrated circuits (“structured ASICs”). The flows may include feeding back design transformations that are performed during either flow so that a later performance of the other flow will necessarily include the same transformations, thereby helping to ensure functional equivalence. The flows may include a comparison of intermediate results in order to prove that functional equivalence is being achieved.
摘要翻译：提供了可产生功能等同的现场可编程门阵列（“FPGA”）和结构化专用集成电路（“结构化ASIC”）的编译器流。流可以包括反馈在任一流程期间执行的设计变换，使得另一流程的稍后的性能将必然包括相同的变换，由此有助于确保功能等同性。流程可以包括中间结果的比较，以证明正在实现功能等同性。

30. 发明授权

US07030652B1 LUT-based logic element with support for Shannon decomposition and associated method 有权
标题翻译：基于LUT的逻辑元素，支持香农分解及相关方法
公开(公告)号：US07030652B1
公开(公告)日：2006-04-18
申请号：US10830819
申请日：2004-04-23
申请人： David Lewis , James Schleicher
发明人： David Lewis , James Schleicher
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , H03K19/1737 , H03K19/177
摘要： A logic circuit comprising: a plurality of logic elements; wherein at least one logic element includes, first and second LUT blocks that includes an output; an output multiplexer that includes first and second inputs, an output, and that includes a control output; a control input multiplexer circuit including a control input and including first and second data inputs that can be configured to receive first and second data outputs provided by one or more other logic elements of the plurality of logic elements and that includes a data output that can be connected to the control input of the output multiplexer; and multiple control inputs that can be shared by the first and second LUT blocks.
摘要翻译：一种逻辑电路，包括：多个逻辑元件; 其中至少一个逻辑元件包括包括输出的第一和第二LUT块; 输出多路复用器，其包括第一和第二输入，输出，并且包括控制输出; 控制输入多路复用器电路，其包括控制输入并且包括第一和第二数据输入，所述第一和第二数据输入可被配置为接收由所述多个逻辑元件的一个或多个其他逻辑元件提供的第一和第二数据输出，并且包括可以是连接到输出多路复用器的控制输入; 以及可由第一和第二LUT块共享的多个控制输入。

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