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21. 发明申请

US20050201181A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20050201181A1
公开(公告)日：2005-09-15
申请号：US11073738
申请日：2005-03-08
申请人： Satoshi Ishikura
发明人： Satoshi Ishikura
IPC分类号： H01L21/822 , G11C5/06 , H01L21/82 , H01L27/04
CPC分类号： H01L27/0207 , G11C5/063 , G11C11/417 , H01L27/105 , H01L27/11 , H01L27/1116
摘要： First and second internal power source lines supply first and second voltages to an internal circuit, respectively. A first line 31 and a second line 32 are arranged parallel to the first and the second internal power source lines in a layer above the layer in which the first and the second internal power source lines are arranged. Third lines 33 extend in a direction perpendicular to the first line in a layer above the layer in which the first and the second internal power source lines are present. Fourth lines 34 extend in a direction perpendicular to the second line in a layer above the layer in which the first and the second internal power source lines are present. The first, and the third and the first internal power source lines are connected, and the second, and the fourth and the second internal power source lines are connected.
摘要翻译：第一和第二内部电源线分别向内部电路提供第一和第二电压。第一线31和第二线32平行于第一和第二内部电源线并排布置在第一和第二内部电源线的层之上的层中。第三线33在其中存在第一和第二内部电源线的层上方的层中沿垂直于第一线的方向延伸。第四条线34在其中存在第一和第二内部电源线的层上方的层中在与第二线垂直的方向上延伸。连接第一和第三和第一内部电源线，并且连接第二和第四和第二内部电源线。

22. 发明授权

US06611950B2 Semiconductor device, semiconductor device design method, semiconductor device design method recording medium, and semiconductor device design support system 有权
公开(公告)号：US06611950B2
公开(公告)日：2003-08-26
申请号：US10278496
申请日：2002-10-23
申请人： Satoshi Ishikura
发明人： Satoshi Ishikura
IPC分类号： G06F1750
CPC分类号： H01L27/118 , G06F17/5072 , G06F17/5077 , H01L24/02 , H01L27/0255 , H01L27/11807 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/30105
摘要： Repeater cells each comprising a buffer or an inverter and an n+ diffusion layer-P well type protection diode or a p+ diffusion layer-N well type antenna protection diode connected to an input pin of the buffer or the inverter for preventing antenna damage or an antenna rule error from occurring are previously registered by registration means 511 as the cells to be registered in a cell library 505. Whether or not a wiring conductor conducting to a gate electrode becomes an antenna ratio exceeding an allowed antenna ratio in the semiconductor device is determined by determination means 514 and if the wiring conductor exceeds the allowable antenna ratio, one or more repeater cells are inserted into any point of the wiring conductor by selection means 515.

23. 发明授权

US08761004B2 Network system 有权
标题翻译：网络系统
公开(公告)号：US08761004B2
公开(公告)日：2014-06-24
申请号：US13376734
申请日：2010-06-14
申请人： Atsuya Yamashita , Shinya Kurosaki , Satoshi Ishikura , Hiroaki Nakajima
发明人： Atsuya Yamashita , Shinya Kurosaki , Satoshi Ishikura , Hiroaki Nakajima
IPC分类号： H04L12/26
CPC分类号： H04L12/462 , H04L41/0668 , H04L43/0811 , H04L69/40
摘要： A link control function unit 506 of a device 500 notifies a counterpart device 600 of a line in which a link disconnection occurs among lines 508 to 510 and L500 terminated at line terminals 501 to 503 or a lower stage line terminal 504 of the self device 500 and the cause of the link disconnection is not a forcible closure of a line terminal of the self device. Further, the link control function unit 506 does not forcibly close the lower stage line terminal 504 of the self device 500 if a line in which a link disconnection occurs, notified from the counterpart device 600, is a line terminated at a lower stage line terminal 604 of the counterpart device 600.
摘要翻译：设备500的链路控制功能单元506向对方设备600通知在自身设备500的线路终端501至503或下级线路终端504处终止的线路508至510和线路500之间发生链路断开的线路并且链路断开的原因不是强制关闭自身设备的线路终端。此外，如果从对方装置600通知的链路断开发生的线路是在下级线路终端处终止的线路，则链路控制功能单元506不强制关闭自身装置500的下级线路终端504 604。

24. 发明申请

US20120106323A1 NETWORK SYSTEM 有权
标题翻译：网络系统
公开(公告)号：US20120106323A1
公开(公告)日：2012-05-03
申请号：US13376734
申请日：2009-06-22
申请人： Atsuya Yamashita , Shinya Kurosaki , Satoshi Ishikura , Hiroaki Nakajima
发明人： Atsuya Yamashita , Shinya Kurosaki , Satoshi Ishikura , Hiroaki Nakajima
IPC分类号： H04L12/26
CPC分类号： H04L12/462 , H04L41/0668 , H04L43/0811 , H04L69/40
摘要： A link control function unit 506 of a device 500 notifies a counterpart device 600 of a line in which a link disconnection occurs among lines 508 to 510 and L500 terminated at line terminals 501 to 503 or a lower stage line terminal 504 of the self device 500 and the cause of the link disconnection is not a forcible closure of a line terminal of the self device. Further, the link control function unit 506 does not forcibly close the lower stage line terminal 504 of the self device 500 if a line in which a link disconnection occurs, notified from the counterpart device 600, is a line terminated at a lower stage line terminal 604 of the counterpart device 600.
摘要翻译：设备500的链路控制功能单元506向对方设备600通知在自身设备500的线路终端501至503或下级线路终端504处终止的线路508至510和线路500之间发生链路断开的线路并且链路断开的原因不是强制关闭自身设备的线路终端。此外，如果从对方装置600通知的链路断开发生的线路是在下级线路终端处终止的线路，则链路控制功能单元506不强制关闭自身装置500的下级线路终端504 604。

25. 发明授权

US07778075B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07778075B2
公开(公告)日：2010-08-17
申请号：US12425018
申请日：2009-04-16
申请人： Satoshi Ishikura , Hironori Akamatsu , Kazuo Itoh , Yoshinobu Yamagami
发明人： Satoshi Ishikura , Hironori Akamatsu , Kazuo Itoh , Yoshinobu Yamagami
IPC分类号： G11C7/10 , G11C5/14 , G11C11/34
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12005 , G11C2029/1202 , G11C2029/1204
摘要： A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to bit lines 106 and 107; a latch potential control circuit 101 for switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin 102; and a read/write control circuit 103 for controlling the potential supplied to the sources of the load transistors 108 and 111 to be lower than at least one of the potential supplied to the word line 105 and the potential supplied to the bit lines 106 and 107, during an arbitrary period of at least a read operation in the test mode.
摘要翻译：半导体存储器件包括具有电路结构的存储单元，其中提供给包含在锁存部分中的负载晶体管108和111的源极的电位与提供给字线105的电位和提供给字线105的电位中的至少一个不同位线106和107; 锁存电位控制电路101，用于根据施加到测试模式设置引脚102的信号将正常操作模式和测试模式切换到彼此; 以及用于控制提供给负载晶体管108和111的源的电位低于提供给字线105的电位和提供给位线106和107的电位中的至少一个的读/写控制电路103 在测试模式下至少读取操作的任意时段期间。

26. 发明授权

US07542368B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07542368B2
公开(公告)日：2009-06-02
申请号：US11634110
申请日：2006-12-06
申请人： Satoshi Ishikura , Hironori Akamatsu , Kazuo Itoh , Yoshinobu Yamagami
发明人： Satoshi Ishikura , Hironori Akamatsu , Kazuo Itoh , Yoshinobu Yamagami
IPC分类号： G11C5/14 , G11C7/00 , G11C7/10 , G11C11/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12005 , G11C2029/1202 , G11C2029/1204
摘要： A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to bit lines 106 and 107; a latch potential control circuit 101 for switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin 102; and a read/write control circuit 103 for controlling the potential supplied to the sources of the load transistors 108 and 111 to be lower than at least one of the potential supplied to the word line 105 and the potential supplied to the bit lines 106 and 107, during an arbitrary period of at least a read operation in the test mode.
摘要翻译：半导体存储器件包括具有电路结构的存储单元，其中提供给包含在锁存部分中的负载晶体管108和111的源极的电位与提供给字线105的电位和提供给字线105的电位中的至少一个不同位线106和107; 锁存电位控制电路101，用于根据施加到测试模式设置引脚102的信号将正常操作模式和测试模式切换到彼此; 以及用于控制提供给负载晶体管108和111的源的电位低于提供给字线105的电位和提供给位线106和107的电位中的至少一个的读/写控制电路103 在测试模式下至少读取操作的任意时段期间。

27. 发明授权

US07114140B2 Semiconductor device, semiconductor device design method, semiconductor device design method recording medium, and semiconductor device design support system 失效
标题翻译：半导体器件，半导体器件设计方法，半导体器件设计方法记录介质和半导体器件设计支持系统
公开(公告)号：US07114140B2
公开(公告)日：2006-09-26
申请号：US10600737
申请日：2003-06-20
申请人： Satoshi Ishikura
发明人： Satoshi Ishikura
IPC分类号： G06F17/50
CPC分类号： H01L27/118 , G06F17/5072 , G06F17/5077 , H01L24/02 , H01L27/0255 , H01L27/11807 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/30105
摘要： Repeater cells each comprising a buffer or an inverter and an n+ diffusion layer-P well type protection diode or a p+ diffusion layer-N well type antenna protection diode connected to an input pin of the buffer or the inverter for preventing antenna damage or an antenna rule error from occurring are previously registered by registration means 511 as the cells to be registered in a cell library 505. Whether or not a wiring conductor conducting to a gate electrode becomes an antenna ratio exceeding an allowed antenna ratio in the semiconductor device is determined by determination means 514 and if the wiring conductor exceeds the allowable antenna ratio, one or more repeater cells are inserted into any point of the wiring conductor by selection means 515.
摘要翻译：每个包括缓冲器或逆变器的中继器单元和连接到缓冲器或逆变器的输入引脚的n +扩散层-P阱型保护二极管或p +扩散层-N阱型天线保护二极管，用于防止天线损坏或天线先前通过注册装置511登记出现规则错误作为登记在单元库505中的单元。由确定装置514确定导体至栅电极的布线导体是否超过半导体器件中的允许天线比率的天线比，并且如果布线导体超过允许天线比率，则将一个或多个中继器单元插入任何通过选择装置515接线导体的点。

28. 发明授权

US06838736B2 Semiconductor device having noise immunity 有权
标题翻译：具有抗噪声的半导体器件
公开(公告)号：US06838736B2
公开(公告)日：2005-01-04
申请号：US09837450
申请日：2001-04-19
申请人： Satoshi Ishikura , Yukio Iijima , Nobuaki Minakuchi
发明人： Satoshi Ishikura , Yukio Iijima , Nobuaki Minakuchi
IPC分类号： H01L21/76 , H01L21/761 , H01L21/762 , H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/08 , H01L27/092 , H01L29/94
CPC分类号： H01L21/761 , H01L21/76229 , H01L21/823878 , H01L27/092
摘要： A semiconductor device, including a dummy diffused layer in the upper part of a substrate, has its noise immunity improved. The dummy diffused layer is formed between analog and digital blocks to eliminate dishing, which usually occurs during a CMP process for defining STI regions. The surface of the dummy diffused layer is covered with an anti-silicidation film at least partially and a dummy gate electrode so as not to be silicided. The dummy gate electrode can be formed along with a normal gate electrode for a transistor. Accordingly, there is no need to add any extra process step to the fabrication process.

29. 发明授权

US06502225B2 Semiconductor device, semiconductor device design method, semiconductor device design method recording medium, and semiconductor device design support system 有权
公开(公告)号：US06502225B2
公开(公告)日：2002-12-31
申请号：US10080740
申请日：2002-02-22
申请人： Satoshi Ishikura
发明人： Satoshi Ishikura
IPC分类号： G06F1750
CPC分类号： H01L27/118 , G06F17/5072 , G06F17/5077 , H01L24/02 , H01L27/0255 , H01L27/11807 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/30105
摘要： Repeater cells each comprising a buffer or an inverter and an n+ diffusion layer-P well type protection diode or a p+ diffusion layer-N well type antenna protection diode connected to an input pin of the buffer or the inverter for preventing antenna damage or an antenna rule error from occurring are previously registered by registration means 511 as the cells to be registered in a cell library 505. Whether or not a wiring conductor conducting to a gate electrode becomes an antenna ratio exceeding an allowed antenna ratio in the semiconductor device is determined by determination means 514 and if the wiring conductor exceeds the allowable antenna ratio, one or more repeater cells are inserted into any point of the wiring conductor by selection means 515.

30. 发明授权

US06421816B1 Semiconductor device, semiconductor device design method, semiconductor device design method recording medium, and semiconductor device design support system 失效
标题翻译：半导体器件，半导体器件设计方法，半导体器件设计方法记录介质和半导体器件设计支持系统
公开(公告)号：US06421816B1
公开(公告)日：2002-07-16
申请号：US09274659
申请日：1999-03-23
申请人： Satoshi Ishikura
发明人： Satoshi Ishikura
IPC分类号： G06F1750
CPC分类号： H01L27/118 , G06F17/5072 , G06F17/5077 , H01L24/02 , H01L27/0255 , H01L27/11807 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/30105
摘要： Repeater cells each comprising a buffer or an inverter and an n+ diffusion layer-P well type protection diode or a p+ diffusion layer-N well type antenna protection diode connected to an input pin of the buffer or the inverter for preventing antenna damage or an antenna rule error from occurring are previously registered by registration means 511 as the cells to be registered in a cell library 505. Whether or not a wiring conductor conducting to a gate electrode becomes an antenna ratio exceeding an allowed antenna ratio in the semiconductor device is determined by determination means 514 and if the wiring conductor exceeds the allowable antenna ratio, one or more repeater cells are inserted into any point of the wiring conductor by selection means 515.
摘要翻译：每个包括缓冲器或逆变器的中继器单元和连接到缓冲器或逆变器的输入引脚的n +扩散层-P阱型保护二极管或p +扩散层-N阱型天线保护二极管，用于防止天线损坏或天线先前通过注册装置511登记的规则错误作为登记在单元库505中的单元。导电至栅电极的布线导体是否超过半导体器件中的允许天线比的天线比是由确定装置514，并且如果布线导体超过允许的天线比率，则通过选择装置515将一个或多个中继器单元插入布线导体的任何点。

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