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21. 发明授权

US06212236B1 Image decoding apparatus 失效
标题翻译：图像解码装置
公开(公告)号：US06212236B1
公开(公告)日：2001-04-03
申请号：US09048190
申请日：1998-03-25
申请人： Hideshi Nishida , Kozo Kimura , Makoto Hirai , Tokuzo Kiyohara
发明人： Hideshi Nishida , Kozo Kimura , Makoto Hirai , Tokuzo Kiyohara
IPC分类号： H04N712
CPC分类号： H04N19/507 , H04N19/61
摘要： Bitstream analyzing unit 111 fetches a coded block pattern and a coded quantized DCT coefficient from each block in a bitstream. Entropy decoding unit 112 decodes the coded block pattern into a block pattern and decodes the coded quantized DCT coefficient into pairs of a run length and an effectiveness factor. Dequantization unit 115 generates orthogonal transformation coefficients from the pairs of a run length and an effectiveness factor. Inverse Discrete Cosine Transform (IDCT) unit 110 generates a difference image from the orthogonal transformation coefficients. Decode controlling unit 110 instructs first selecting unit 118 to select constants “0”output from first constant generating unit 117 when the image is a “skipped” block. Image storage unit 120 stores a plurality of reference frame pictures having been decoded. Image restoring unit 119 restores an original block by adding a decoded difference image to a reference block read from the reference frame pictures stored in the image storage unit 120.
摘要翻译：比特流分析单元111从比特流中的每个块获取编码块模式和编码的量化DCT系数。熵解码单元112将编码块模式解码为块模式，并将编码的量化DCT系数解码为游程长度和有效性因子对。去量化单元115从游程长度和有效性因子的对生成正交变换系数。逆离散余弦变换（IDCT）单元110从正交变换系数生成差分图像。当图像为“跳过”块时，解码控制单元110指示第一选择单元118选择从第一常数生成单元117输出的常数“0”。图像存储单元120存储已被解码的多个参考帧图像。图像恢复单元119通过将解码的差异图像添加到从存储在图像存储单元120中的参考帧图像中读取的参考块来恢复原始块。

22. 发明授权

US10230991B2 Signal-processing apparatus including a second processor that, after receiving an instruction from a first processor, independantly controls a second data processing unit without further instrcuction from the first processor 有权
公开(公告)号：US10230991B2
公开(公告)日：2019-03-12
申请号：US12179873
申请日：2008-07-25
申请人： Tomonori Kataoka , Hideshi Nishida , Kouzou Kimura , Nobuo Higaki , Tokuzo Kiyohara
发明人： Tomonori Kataoka , Hideshi Nishida , Kouzou Kimura , Nobuo Higaki , Tokuzo Kiyohara
IPC分类号： G06F9/38 , H04N19/86 , H04N19/61 , H04N19/44 , H04N19/42 , H04N19/436 , H04N19/523
摘要： A signal-processing apparatus includes an instruction-parallel processor, a first data-parallel processor, a second data-parallel processor, and a motion detection unit, a de-blocking filtering unit and a variable-length coding/decoding unit which are dedicated hardware. With this structure, during signal processing of an image compression and decompression algorithm needing a large amount of processing, the load is distributed between software and hardware, so that the signal-processing apparatus can realize high processing capability and flexibility.

23. 发明授权

US08006076B2 Processor and program execution method capable of efficient program execution 有权
公开(公告)号：US08006076B2
公开(公告)日：2011-08-23
申请号：US12110491
申请日：2008-04-28
申请人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
发明人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/48 , G06F9/52
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

24. 发明申请

US20090049219A1 INFORMATION PROCESSING APPARATUS AND EXCEPTION CONTROL CIRCUIT 有权
标题翻译：信息处理设备和异常控制电路
公开(公告)号：US20090049219A1
公开(公告)日：2009-02-19
申请号：US11658816
申请日：2005-08-19
申请人： Hideshi Nishida , Takeshi Furuta , Tetsuya Tanaka , Kozo Kimura , Tokuzo Kiyohara
发明人： Hideshi Nishida , Takeshi Furuta , Tetsuya Tanaka , Kozo Kimura , Tokuzo Kiyohara
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F9/30101 , G06F9/3861 , G06F9/3879 , G06F9/4812 , G06F2209/481
摘要： To provide an information processing apparatus capable of performing switching between an exception handler and normal processing, the information processing apparatus comprising: An information processing apparatus comprising: a processor; a data processing unit operable to perform particular processing upon receiving a processing request from the processor; an interrupt controller operable to issue an interrupt request to the processor; and an exception control unit operable to control the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line, the data processing unit includes a notification unit operable to notify, via the dedicated line, the exception control unit of status information showing a current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.
摘要翻译：为了提供能够执行异常处理程序与正常处理之间的切换的信息处理装置，所述信息处理装置包括：信息处理装置，包括：处理器; 数据处理单元，用于在从所述处理器接收到处理请求时执行特定处理; 中断控制器，用于向所述处理器发出中断请求; 以及异常控制单元，其可操作以控制所述中断控制器，其中所述数据处理单元经由专用线与所述异常控制单元连接，所述数据处理单元包括通知单元，用于经由所述专用线通知所述异常控制单元表示数据处理单元的当前状态的状态信息，并且基于所通知的状态信息和由处理器设置的设置信息，异常控制单元判断是否使中断控制器发出中断请求以执行异常处理程序处理器。

25. 发明授权

US06901454B2 Circuit group control system 有权
标题翻译：电路组控制系统
公开(公告)号：US06901454B2
公开(公告)日：2005-05-31
申请号：US10289993
申请日：2002-11-07
申请人： Nobuo Higaki , Tetsuya Tanaka , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida
发明人： Nobuo Higaki , Tetsuya Tanaka , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida
IPC分类号： G06F9/38 , G06F3/00 , G06F9/46 , G06F9/48 , G06F13/28 , G06F15/16 , G06F15/167 , G06F15/80
CPC分类号： G06F9/4843
摘要： A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.
摘要翻译：一种电路组控制系统，其从主处理器接收第一命令序列和第二命令序列，每个命令序列由多个命令组成，每个命令由多个电路中的一个执行，并且使任何可用的电路按照每个命令序列中的排列顺序逐个执行命令。电路组控制系统通过使电路（第二电路）在第二命令序列中执行命令而实现多个命令序列的并发执行，而另一电路（第一电路）在第一命令序列中执行另一命令。

26. 发明申请

US20050053290A1 Video decoding apparatus 审中-公开
标题翻译：视频解码装置
公开(公告)号：US20050053290A1
公开(公告)日：2005-03-10
申请号：US10896150
申请日：2004-07-21
申请人： Yoshiyuki Wada , Kosuke Yoshioka , Hideshi Nishida
发明人： Yoshiyuki Wada , Kosuke Yoshioka , Hideshi Nishida
IPC分类号： H04N7/26 , H04N7/36 , G06K9/36
CPC分类号： H04N19/44 , H04N19/51 , H04N19/563
摘要： A decoding apparatus lightens the load incurred by padding processing. When the decoding apparatus outputs decoded data to a frame memory, a padding unit in the decoding apparatus judges whether the decoded data includes boundary pixels, and when boundary pixels are judged to be included, performs padding processing to an extension area using boundary pixel data. As a result, as well as pixels in one decoded macroblock being output, when boundary pixels are included in the output macroblock, the boundary pixels are output to the extension area. This eliminates the need to re-read the boundary pixels from the frame memory.
摘要翻译：解码装置减轻由填补处理引起的负担。当解码装置将解码数据输出到帧存储器时，解码装置中的填补单元判断解码数据是否包括边界像素，并且当判定包括边界像素时，使用边界像素数据对扩展区域进行填充处理。结果，当输出一个解码宏块中的像素时，当输出宏块中包含边界像素时，将边界像素输出到扩展区域。这消除了从帧存储器重新读取边界像素的需要。

27. 发明授权

US06829302B2 Pixel calculating device 有权
标题翻译：像素计算装置
公开(公告)号：US06829302B2
公开(公告)日：2004-12-07
申请号：US10019498
申请日：2001-12-20
申请人： Hiroyuki Morishita , Kosuke Yoshioka , Hideshi Nishida , Makoto Hirai , Ryuji Matsuura , Toshiaki Tsuji , Kozo Kimura , Tokuzo Kiyohara
发明人： Hiroyuki Morishita , Kosuke Yoshioka , Hideshi Nishida , Makoto Hirai , Ryuji Matsuura , Toshiaki Tsuji , Kozo Kimura , Tokuzo Kiyohara
IPC分类号： H04N712
CPC分类号： H04N19/80 , G06T3/4007 , G06T3/4023 , G06T5/20 , G06T2200/28
摘要： A pixel calculating device that performs vertical filtering on pixel data in order to reduce frame data in a vertical direction. The pixel calculating device includes a decoding unit 401 for decoding compressed video data to produce frame data, frame memory 402 for storing the frame data, a filtering unit 403 for reducing the frame data in a vertical direction by the vertical filtering to produce a reduced image, buffer memory 404 for storing the reduced image outputted from filtering unit 403, and a control unit 406 for controlling filtering unit 403 based on a decoding state of the video data by decoding unit 401 and a filtering state of the frame data by filtering unit 403, so that overrun and underrun do not occur in filtering unit 403.
摘要翻译：一种对像素数据进行垂直滤波以便在垂直方向上减少帧数据的像素计算装置。像素计算装置包括用于解码压缩视频数据以产生帧数据的解码单元401，用于存储帧数据的帧存储器402，用于通过垂直滤波减少垂直方向上的帧数据以产生缩小图像的滤波单元403 用于存储从滤波单元403输出的缩小图像的缓冲存储器404，以及基于解码单元401的视频数据的解码状态和滤波单元403的帧数据的滤波状态来控制滤波单元403的控制单元406 ，因此在过滤单元403中不会发生溢出和欠载。

28. 发明授权

US06809777B2 Pixel calculating device 有权
标题翻译：像素计算装置
公开(公告)号：US06809777B2
公开(公告)日：2004-10-26
申请号：US10019419
申请日：2001-12-18
申请人： Hiroyuki Oka , Hideshi Nishida , Kosuke Yoshioka , Tokuzo Kiyohara , Makoto Hirai , Kozo Kimura , Ryuji Matsuura , Hiroyuki Morishita , Toshiaki Tsuji
发明人： Hiroyuki Oka , Hideshi Nishida , Kosuke Yoshioka , Tokuzo Kiyohara , Makoto Hirai , Kozo Kimura , Ryuji Matsuura , Hiroyuki Morishita , Toshiaki Tsuji
IPC分类号： H04N964
CPC分类号： H04N19/80 , G06T1/20 , G06T5/20
摘要： A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group 22 storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supplied from input buffer group 22, and then acquires pixel data from an adjacent pixel processing unit. Further operations are performed by each of the pixel processing units using the acquired pixel data and operation results are accumulated. Filtering is carried out through a repetition of this acquiring and accumulation process, the number of taps being determined by the number of repetitions.
摘要翻译：用于执行垂直滤波的像素计算装置，其包括16个像素处理单元1至16以及存储16个像素数据和滤波器系数的输入缓冲器组22。每个像素处理单元使用从输入缓冲器组22提供的像素数据和滤波器系数来执行操作，然后从邻近的像素处理单元获取像素数据。使用所获取的像素数据由每个像素处理单元执行进一步的操作，并且累积运算结果。通过重复该获取和累积过程来进行过滤，抽头的数量由重复次数确定。

29. 发明授权

US09426412B2 Rendering device and rendering method 有权
标题翻译：渲染设备和渲染方法
公开(公告)号：US09426412B2
公开(公告)日：2016-08-23
申请号：US13819770
申请日：2012-05-21
申请人： Hideshi Nishida
发明人： Hideshi Nishida
IPC分类号： H04N7/01 , G09G5/14 , G09G5/393 , G09G5/395 , H04N21/431 , H04N5/445 , H04N21/426 , H04N21/4402 , G09G5/02 , G09G5/373 , G09G5/391 , G06T3/40
CPC分类号： H04N7/0117 , G06T3/4092 , G09G5/026 , G09G5/14 , G09G5/373 , G09G5/391 , G09G5/393 , G09G5/395 , G09G2340/0442 , G09G2340/10 , G09G2354/00 , H04N5/44504 , H04N21/42653 , H04N21/4314 , H04N21/440263
摘要： A rendering device provides improved rendering responsiveness in multi-window display for rendering scenarios in which display sizes of images vary over time, while also reducing required memory bandwidth. The device comprises: a scenario processor 101 for interpreting a rendering scenario and calculating for each frame period a scale-down ratio for each of a plurality of pictures; a plurality of decoders 107 for decoding encoded data of a plurality of videos; a plurality of first scalers for scaling-down the decoded pictures using the scale-down ratios calculated by the scenario processor 101; a memory 106 for storing the scaled-down pictures; a plurality of second scalers 113 for reading the scaled-down pictures from the memory and re-scaling the scaled-down pictures to match the scale-down ratios calculated by the scenario processor for a current frame period; and, a composing unit 115 for composing the re-scaled pictures.
摘要翻译：渲染设备在多窗口显示中提供改进的渲染响应性，用于渲染场景，其中图像的显示尺寸随时间变化，同时还减少所需的存储器带宽。该装置包括：场景处理器101，用于解释渲染场景，并为每个帧周期计算多个图像中的每一个的缩小比例; 多个解码器107，用于解码多个视频的编码数据; 多个第一缩放器，用于使用由所述情景处理器101计算的缩小比例来缩小所述解码图像; 用于存储缩小图像的存储器106; 多个第二定标器113，用于从存储器读取按比例缩小的图像，并重新缩放缩小图像以匹配由场景处理器为当前帧周期计算的缩小比例; 以及组合单元115，用于组合重新缩放的图片。

30. 发明授权

US08719827B2 Processor and program execution method capable of efficient program execution 有权
标题翻译：处理器和程序执行方法能够高效地执行程序
公开(公告)号：US08719827B2
公开(公告)日：2014-05-06
申请号：US13179614
申请日：2011-07-11
申请人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
发明人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/46 , G06F9/00 , G06F1/00
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.
摘要翻译：一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

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