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21. 发明授权

US4716307A Regulated power supply for semiconductor chips with compensation for changes in electrical characteristics or chips and in external power supply 失效
标题翻译：用于半导体芯片的稳压电源，可补偿电气特性或芯片以及外部电源的变化
公开(公告)号：US4716307A
公开(公告)日：1987-12-29
申请号：US895730
申请日：1986-08-12
申请人： Keizo Aoyama
发明人： Keizo Aoyama
IPC分类号： H03G3/00 , G05F1/46 , H01L21/822 , H01L27/04 , H01L27/06 , H03G3/30 , G05F1/56 , G05F5/08
CPC分类号： G05F1/465
摘要： A semiconductor device having a circuit for regulating the external power supply voltage applied to the chip. When numerous chips are used in an electronic circuit having an external power supply voltage, variations in the electrical characteristics, such as the total power supply current, of each chip, become a problem. According to the present invention, variations in the electrical characteristics can be reduced by compensating the chip-to-chip fluctuations of the conductance of transistors (FETs) contained in an inner circuit disposed on the chip. A dummy transistor having a relatively short channel length is employed as a circuit for detecting the electrical characteristics of the transistors formed on the chip. The voltage drop across the dummy transistor is employed as a representative signal since it is sensitive to variations in the characteristics of the FETs contained in the inner circuit. Regulation of the power supply voltage is performed by a regulating device, usually a transistor, connected in series between the external power supply and the inner circuit. The representative signal is amplified by a regulating signal generating circuit whose output voltage is applied to the regulating device, thereby controlling the conductance of the regulating device.
摘要翻译：一种具有用于调节施加到芯片的外部电源电压的电路的半导体器件。当在具有外部电源电压的电子电路中使用许多芯片时，每个芯片的电特性（例如总电源电流）的变化成为问题。根据本发明，通过补偿芯片上布置的内部电路中包含的晶体管（FET）的电导的芯片间的波动，可以减小电特性的变化。采用具有较短沟道长度的虚设晶体管作为用于检测芯片上形成的晶体管的电特性的电路。虚拟晶体管两端的电压降用作代表性信号，因为它对包含在内部电路中的FET的特性的变化敏感。电源电压的调节由外部电源和内部电路串联连接的调节装置（通常是晶体管）来执行。代表信号由输出电压施加到调节装置的调节信号发生电路放大，从而控制调节装置的电导。

22. 发明授权

US4656608A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4656608A
公开(公告)日：1987-04-07
申请号：US737076
申请日：1985-05-23
申请人： Keizo Aoyama
发明人： Keizo Aoyama
IPC分类号： G11C11/41 , G11C7/12 , G11C8/00 , G11C8/18 , G11C11/34 , H01L27/00 , G11C7/00
CPC分类号： G11C11/34 , G11C7/12 , G11C8/00 , G11C8/18
摘要： A semiconductor memory device includes at least a pair of bit lines, a word line, a pair of load transistors each connected to the bit lines, a memory cell connected to the bit lines and the word line and selected by an address signal, and an equalizing circuit connected between each of the bit lines. According to the present invention, the equalizing circuit comprises an P-channel type MIS transistor and an N-channel type MIS transistor that are connected in parallel and temporarily turned ON in response to a change of the address signal.
摘要翻译：半导体存储器件包括至少一对位线，字线，每个连接到位线的一对负载晶体管，连接到位线和字线并由地址信号选择的存储单元，以及连接在每个位线之间的均衡电路。根据本发明，均衡电路包括响应于地址信号变化而并联并暂时导通的P沟道型MIS晶体管和N沟道型MIS晶体管。

23. 发明授权

US4616344A Static memory circuit 失效
标题翻译：静态存储电路
公开(公告)号：US4616344A
公开(公告)日：1986-10-07
申请号：US536880
申请日：1983-09-29
申请人： Eiji Noguchi , Keizo Aoyama
发明人： Eiji Noguchi , Keizo Aoyama
IPC分类号： G11C11/417 , G11C7/12 , G11C11/41 , G11C11/419 , G11C7/00
CPC分类号： G11C7/12 , G11C11/419
摘要： A static memory circuit includes memory cells arranged in a matrix of word lines and bit lines, and a reset circuit for resetting each pair of bit lines to have an equivalent potential in response to a change in a row address signal. The reset circuit generates a reset signal at a first time a certain time period after a first change of the row address signal and terminates the reset signal at a second time when a second change of the row address signal is detected. Thus, data destruction during reading is prevented.
摘要翻译：静态存储器电路包括以字线和位线的矩阵形式布置的存储器单元，以及复位电路，用于根据行地址信号的变化将每对位线复位为具有等效电位。复位电路在行地址信号的第一次更改之后的特定时间段的第一时间产生复位信号，并且当检测到行地址信号的第二次改变时，在第二时间终止复位信号。因此，可以防止读取期间的数据破坏。

24. 发明申请

US20110295761A1 BUSINESS FORM MANAGEMENT SYSTEM, METHOD AND PROGRAM 审中-公开
标题翻译：业务表单管理系统，方法和程序
公开(公告)号：US20110295761A1
公开(公告)日：2011-12-01
申请号：US13117679
申请日：2011-05-27
申请人： Akiyoshi Sudo , Keizo Aoyama , Tsuneo Watanabe , Hideyuki Kobayashi , Keiko Ootani
发明人： Akiyoshi Sudo , Keizo Aoyama , Tsuneo Watanabe , Hideyuki Kobayashi , Keiko Ootani
IPC分类号： G06Q10/00
CPC分类号： G06Q50/04 , G06F17/243 , G06Q10/10 , G06Q50/06 , Y02P90/30
摘要： According to one embodiment, a server has a first storage, a second storage, a built-in business form modification part, download execution part, and search part. The download execution part transmits the objective business form and the business form generation program stored in the first and second storage to a user terminal. The search part searches for the plant data in response to a request from the user terminal and transmits the data to the terminal. The business form generation program includes a business form definition program and a data expansion program. The business form definition program sets search conditions of plant data in the objective business form. The data expansion program requests the server to search for the plant data that satisfies the search conditions in the objective business form and outputs the plant data to the objective business form. The user terminal has an objective business form editing part and a business form generation part. The objective business form editing part edits an objective business form transmitted from the download execution part. The business form generation part executes the business form generation program to output the plant data to the edited objective business form.
摘要翻译：根据一个实施例，服务器具有第一存储器，第二存储器，内置业务表单修改部件，下载执行部件和搜索部件。下载执行部将存储在第一和第二存储器中的业务表单生成程序发送到用户终端。搜索部件响应于来自用户终端的请求搜索工厂数据，并将数据发送到终端。业务表单生成程序包括业务表单定义程序和数据扩展程序。业务形式定义程序以客观业务形式设置工厂数据的搜索条件。数据扩展程序请求服务器搜索符合目标业务形式的搜索条件的工厂数据，并将工厂数据输出到客观业务表单。用户终端具有客观的业务表单编辑部分和业务表单生成部分。客观业务表单编辑部分编辑从下载执行部分发送的客观业务表单。业务表单生成部分执行业务表单生成程序，将工厂数据输出到编辑的客户业务表单。

25. 发明授权

US5335199A Multiport memory 失效
标题翻译：多端口内存
公开(公告)号：US5335199A
公开(公告)日：1994-08-02
申请号：US853788
申请日：1992-03-19
申请人： Keizo Aoyama
发明人： Keizo Aoyama
IPC分类号： G11C7/10 , G11C8/16 , G11C13/00
CPC分类号： G11C8/16 , G11C7/1075
摘要： A multiport memory that allows simultaneous reading and/or writing to the same memory cells by shorting selected bit lines with other bit lines of cells whose row address from each port match.
摘要翻译：通过与来自每个端口的行地址匹配的单元格的其他位线短路所选位线，允许同时读取和/或写入相同存储器单元的多端口存储器。

26. 发明授权

US5317536A Dual-port type semiconductor integrated memory circuit 失效
标题翻译：双端口型半导体集成存储电路
公开(公告)号：US5317536A
公开(公告)日：1994-05-31
申请号：US840127
申请日：1992-02-24
申请人： Keizo Aoyama
发明人： Keizo Aoyama
IPC分类号： G11C11/41 , G11C7/12 , G11C8/16 , G11C11/412 , G11C11/418 , G11C7/00
CPC分类号： G11C7/12 , G11C8/16
摘要： A dual-port memory circuit includes a memory cell having a pair of nodes, a first port having a first pair of bit lines and a first word line connected to said memory cell, and a second port having a second pair of bit lines and a second word line connected to said memory cell. A detection circuit detects that data is written from one of the first and second ports in a state where the memory cell is selected by both the first and second ports. A control circuit decreases a potential of one of the nodes in response to a detection output of the detection circuit.
摘要翻译：双端口存储器电路包括具有一对节点的存储单元，具有第一对位线的第一端口和连接到所述存储单元的第一字线，以及具有第二对位线的第二端口和连接到所述存储单元的第二字线。在由第一和第二端口二者选择存储单元的状态下，检测电路检测数据是从第一和第二端口之一写入的。响应于检测电路的检测输出，控制电路减小节点之一的电位。

27. 发明授权

US4733377A Asynchronous semiconductor memory device 失效
标题翻译：异步半导体存储器件
公开(公告)号：US4733377A
公开(公告)日：1988-03-22
申请号：US536325
申请日：1983-09-27
申请人： Keizo Aoyama , Kenji Agatsuma , Yasuaki Suzuki
发明人： Keizo Aoyama , Kenji Agatsuma , Yasuaki Suzuki
IPC分类号： G11C11/41 , G11C8/00 , G11C8/18 , H03K19/003
CPC分类号： H03K19/00361 , G11C8/00 , G11C8/18
摘要： An asynchronous semiconductor memory device having an address change detector which generates a pulse with a specified pulse width by detecting change in an address signal and a component for holding an internal circuit in the non-operating condition responding to the address signal for a period when said pulse does not exist. The internal circuit is caused not to operate in response to an unwanted address signal generated in the course of the change of the address signal input from an external device, or in response to an unwanted address signal generated by noise. Thereby power consumption is reduced.
摘要翻译：一种异步半导体存储器件，具有地址变化检测器，其通过检测地址信号中的变化产生具有指定脉冲宽度的脉冲，以及用于在所述非操作状态下响应于所述地址信号保持内部电路的分量，脉冲不存在。使得内部电路不响应于在从外部设备输入的地址信号变化的过程中产生的不需要的地址信号，或响应于由噪声产生的不需要的地址信号而不工作。从而降低功耗。

28. 发明授权

US4730280A Semiconductor memory device having sense amplifiers with different driving abilities 失效
标题翻译：具有不同驱动能力的读出放大器的半导体存储器件
公开(公告)号：US4730280A
公开(公告)日：1988-03-08
申请号：US798783
申请日：1985-11-18
申请人： Keizo Aoyama
发明人： Keizo Aoyama
IPC分类号： G11C11/34 , G11C11/40 , G11C11/4076 , G11C11/4091 , G11C11/4097 , G11C7/00
CPC分类号： G11C11/4076 , G11C11/4091 , G11C11/4097
摘要： A semiconductor memory device, whose pairs of bit lines are connected to a pair of data buses, are divided into a plurality of blocks each comprising a plurality of parted memory cells, a pair of switching elements, and a block sense amplifier. The block sense amplifier has different driving abilities respectively so that the sense amplifier in the farthest block from the data bus has the most driving ability, the sense amplifier in the block nearer to the data bus has less driving ability, and the sense amplifier in the nearest block to the data bus has the least sensing ability. There is only one sense amplifier activated in a selected block, which is a block having a memory cell to be accessed. The operation of the pair of switching elements in a respective block is made after the sense amplifier in the selected block is activated so that the pairs of switching elements in the selected block and the blocks closer to the data bus looking from the selected block are turned ON.
摘要翻译：将一对位线连接到一对数据总线的半导体存储器件被分成多个块，每个块包括多个分离存储单元，一对开关元件和块读出放大器。块读出放大器分别具有不同的驱动能力，使得距离数据总线最远的块中的读出放大器具有最大的驱动能力，靠近数据总线的块中的读出放大器具有较少的驱动能力，而读出放大器在最接近数据总线的块传感能力最小。在所选择的块中仅激活一个读出放大器，该块是具有要存取的存储单元。在所选块中的读出放大器被激活之后，在所选块中的开关元件对之间进行相应块中的开关元件的操作，使得所选块中的开关元件对和从所选块更靠近数据总线的块被转动上。

29. 发明授权

US4578778A Semiconductor memory with load controlling feedback means to reduce power consumption 失效
标题翻译：具有负载控制反馈的半导体存储器意味着降低功耗
公开(公告)号：US4578778A
公开(公告)日：1986-03-25
申请号：US413752
申请日：1982-09-01
申请人： Keizo Aoyama
发明人： Keizo Aoyama
IPC分类号： G11C11/419 , G11C7/00 , G11C11/40
CPC分类号： G11C11/419
摘要： A semiconductor memory circuit including a pair of feedback means. The feedback means are connected between pairs of conventional bit lines and control gates of conventional load transistors. The feedback means control the on or off state of these load transistors in accordance with the logic states of the pair of bit lines.
摘要翻译：一种半导体存储器电路，包括一对反馈装置。反馈装置连接在常规位线对和常规负载晶体管的控制栅极之间。反馈意味着根据该对位线的逻辑状态来控制这些负载晶体管的导通或截止状态。

30. 发明授权

US4480321A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4480321A
公开(公告)日：1984-10-30
申请号：US411008
申请日：1982-08-24
申请人： Keizo Aoyama
发明人： Keizo Aoyama
IPC分类号： G11C11/41 , G11C7/22 , G11C8/18 , G11C11/413 , G11C11/419 , G11C11/40
CPC分类号： G11C7/22 , G11C11/419 , G11C8/18
摘要： A semiconductor memory device, such as a metal-insulator semiconductor random access memory device, in which erroneous write in which may occur when an input address signal is switched, is prevented. The semiconductor memory device comprises an input/output circuit, having an input circuit portion which receives input data and supplies the input data to a pair of data buses and an output circuit portion which amplifies signals from the pair of data buses and outputs therefrom, and a circuit for detecting a change in input address signal and generating a pulse having a predetermined pulse width when the input address signal changes. The input circuit portion of the input/output circuit operates so as to inhibit the writing in of data during generation of the pulse even if the write-enable signal is supplied to the memory device and operates in accordance with the write-enable signal when the pulse is not generated.
摘要翻译：防止在输入地址信号被切换时可能发生错误写入的诸如金属 - 绝缘体半导体随机存取存储器件的半导体存储器件。半导体存储器件包括输入/输出电路，具有输入电路部分，其接收输入数据并将输入数据提供给一对数据总线;以及输出电路部分，放大来自该对数据总线的信号及其输出;以及用于当输入地址信号改变时，检测输入地址信号的变化并产生具有预定脉冲宽度的脉冲的电路。输入/输出电路的输入电路部分工作，以便即使写入使能信号被提供给存储器件并且当写入使能信号在写入使能信号时脉冲不产生。

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