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21. 发明授权

US09263546B2 Method of fabricating a gate dielectric layer 有权
标题翻译：制造栅极电介质层的方法
公开(公告)号：US09263546B2
公开(公告)日：2016-02-16
申请号：US14585802
申请日：2014-12-30
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Wei-Yang Lee , Xiong-Fei Yu , Da-Yuan Lee , Kuang-Yuan Hsu
IPC分类号： H01L29/04 , H01L29/10 , H01L29/66 , H01L29/423 , H01L21/8238 , H01L21/28 , H01L29/51
CPC分类号： H01L29/66477 , H01L21/28185 , H01L21/823857 , H01L29/42368 , H01L29/513 , H01L29/66545
摘要： A method of making a semiconductor device, the method includes forming an active region in a substrate. The method further includes forming a first gate structure over the active region, where the forming the first gate structure includes forming a first interfacial layer. An entirety of a top surface of the first interfacial layer is a curved convex surface. Furthermore, the method includes forming a first high-k dielectric over the first interfacial layer. Additionally, the method includes forming a first gate electrode over a first portion of the first high-k dielectric and surrounded by a second portion of the first high-k dielectric.
摘要翻译：一种制造半导体器件的方法，所述方法包括在衬底中形成有源区。该方法还包括在有源区上形成第一栅极结构，其中形成第一栅极结构包括形成第一界面层。第一界面层的整个顶面是弯曲的凸面。此外，该方法包括在第一界面层上形成第一高k电介质。另外，该方法包括在第一高k电介质的第一部分上形成第一栅极，并被第一高k电介质的第二部分包围。

22. 发明申请

US20150311205A1 SEMICONDUCTOR DEVICE WITH METAL GATE 有权
标题翻译：带金属栅的半导体器件
公开(公告)号：US20150311205A1
公开(公告)日：2015-10-29
申请号：US14792352
申请日：2015-07-06
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Da-Yuan Lee , Kuang-Yuan Hsu
IPC分类号： H01L27/092
CPC分类号： H01L27/0922 , H01L21/823842 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/78
摘要： A semiconductor device including a first gate structure is disposed on the semiconductor substrate. The first gate structure includes a gate dielectric layer, an etch stop layer, a first work function metal, a second work function metal, and a fill metal. A second gate structure is also disposed on the semiconductor substrate. The second gate structure includes the gate dielectric layer, a second work function metal, and the fill metal. In an embodiment, the second gate structure also includes an etch stop layer.
摘要翻译：包括第一栅极结构的半导体器件设置在半导体衬底上。第一栅极结构包括栅极介电层，蚀刻停止层，第一功函数金属，第二功函数金属和填充金属。第二栅极结构也设置在半导体衬底上。第二栅极结构包括栅极介电层，第二功函数金属和填充金属。在一个实施例中，第二栅极结构还包括蚀刻停止层。

23. 发明申请

US20150155234A1 Interconnect Structure and Method for Forming the Same 审中-公开
标题翻译：互连结构及其形成方法
公开(公告)号：US20150155234A1
公开(公告)日：2015-06-04
申请号：US14615264
申请日：2015-02-05
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Po-Cheng Shih , Joung-Wei Liou , Chih-Hung Sun , Chia-Cheng Chou , Kuang-Yuan Hsu
IPC分类号： H01L23/522 , H01L21/768 , H01L23/532
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76807 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L21/76849 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures and methods for forming the same are described. A method for forming an interconnect structure may include: forming a low-k dielectric layer over a substrate; forming an opening in the low-k dielectric layer; forming a conductor in the opening; forming a capping layer over the conductor; and forming an etch stop layer over the capping layer and the low-k dielectric layer, wherein the etch stop layer has a dielectric constant ranging from about 5.7 to about 6.8.
摘要翻译：描述了用于形成相互连接的结构和方法。形成互连结构的方法可以包括：在衬底上形成低k电介质层; 在低k电介质层中形成开口; 在开口中形成导体; 在导体上形成覆盖层; 以及在所述覆盖层和所述低k电介质层上形成蚀刻停止层，其中所述蚀刻停止层的介电常数范围为约5.7至约6.8。

24. 发明申请

US20150056802A1 INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：互连结构及其形成方法
公开(公告)号：US20150056802A1
公开(公告)日：2015-02-26
申请号：US13974430
申请日：2013-08-23
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Po-Cheng Shih , Joung-Wei Liou , Chih-Hung Sun , Chia Cheng Chou , Kuang-Yuan Hsu
IPC分类号： H01L21/768
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76807 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L21/76849 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of an interconnect structure and methods for forming an interconnect structure are provided. The method includes forming a low-k dielectric layer over a substrate, forming an opening in the low-k dielectric layer, forming a conductor in the opening, forming a capping layer over the conductor, and forming an etch stop layer over the capping layer and the low-k dielectric layer. The etch stop layer includes an N element with a content ratio not less than about 25 at %.
摘要翻译：提供了互连结构的实施例和用于形成互连结构的方法。该方法包括在衬底上形成低k电介质层，在低k电介质层中形成开口，在开口中形成导体，在导体上形成覆盖层，并在覆盖层上形成蚀刻停止层和低k电介质层。蚀刻停止层包括含量比不小于约25原子％的N元素。

25. 发明申请

US20150054170A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150054170A1
公开(公告)日：2015-02-26
申请号：US13973626
申请日：2013-08-22
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chung-Chi Ko , Pei-Wen Huang , Chih-Hao Chen , Kuang-Yuan Hsu , Tze-Liang Lee
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/5329 , H01L21/76801 , H01L21/76807 , H01L21/76831 , H01L21/76832 , H01L21/76835 , H01L21/76846 , H01L21/76885 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes conductive features disposed over a workpiece, each conductive feature including a conductive line portion and a via portion. A barrier layer is disposed on sidewalls of each conductive feature and on a bottom surface of the via portion of each conductive feature. The barrier layer includes a dielectric layer. A first insulating material layer is disposed beneath a portion of the conductive line portion of each conductive feature. A second insulating material layer is disposed between the conductive features. A third insulating material layer is disposed beneath the first insulating material layer and the second insulating material layer. A lower portion of the via portion of each of the conductive features is formed within the third insulating material layer. The second insulating material layer has a lower dielectric constant than a dielectric constant of the first insulating material layer and a dielectric constant of the third insulating material layer.
摘要翻译：公开了半导体器件及其制造方法。在一些实施例中，半导体器件包括设置在工件上方的导电特征，每个导电特征包括导线部分和通孔部分。阻挡层设置在每个导电特征的侧壁上并且在每个导电特征的通孔部分的底表面上。阻挡层包括电介质层。第一绝缘材料层设置在每个导电特征的导电线部分的一部分之下。第二绝缘材料层设置在导电特征之间。第三绝缘材料层设置在第一绝缘材料层和第二绝缘材料层的下方。每个导电特征的通孔部分的下部形成在第三绝缘材料层内。第二绝缘材料层具有比第一绝缘材料层的介电常数和第三绝缘材料层的介电常数低的介电常数。

26. 发明申请

US20150017796A1 TECHNIQUES PROVIDING METAL GATE DEVICESWITH MULTIPLE BARRIER LAYERS 有权
标题翻译：通过多个障碍层提供金属栅极设备的技术
公开(公告)号：US20150017796A1
公开(公告)日：2015-01-15
申请号：US14497639
申请日：2014-09-26
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Xiong-Fei Yu , Chun-Yuan Chou , Da-Yuan Lee , Kuang-Yuan Hsu , Jeff J. Xu
IPC分类号： H01L29/49 , H01L21/285 , H01L21/768 , H01L21/3205 , H01L29/66 , H01L29/51
CPC分类号： H01L27/092 , H01L21/28088 , H01L21/2855 , H01L21/28556 , H01L21/32051 , H01L21/76843 , H01L21/76846 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823842 , H01L29/165 , H01L29/4966 , H01L29/512 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7848
摘要： A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
摘要翻译：公开了一种具有金属栅极的半导体器件。具有金属栅极的示例性半导体器件包括半导体衬底，半导体衬底上的源极和漏极特征，半导体衬底上的栅极堆叠并且设置在源极和漏极特征之间。所述栅堆叠包括形成在所述半导体衬底上的HK电介质层，形成在所述HK电介质层的顶部上的金属化合物的多个势垒层，其中每个所述阻挡层具有不同的化学组成; 以及沉积在所述多个阻挡层上的一叠金属栅极层。

27. 发明授权

US08575727B2 Gate structures 有权
标题翻译：门结构
公开(公告)号：US08575727B2
公开(公告)日：2013-11-05
申请号：US13886123
申请日：2013-05-02
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Peng-Soon Lim , Chia-Pin Lin , Kuang-Yuan Hsu
IPC分类号： H01L29/06
CPC分类号： H01L27/092 , H01L27/088 , H01L29/517 , H01L29/66545 , H01L29/66795 , H01L29/78 , H01L29/785
摘要： A semiconductor device is provided. The device includes a semiconductor substrate, first and second projections extending upwardly from the substrate, the projections having respective first and second channel regions therein, and a first gate structure engaging the first projection adjacent the first channel region. The first gate structure includes a first dielectric material over the first channel region, a first opening over the first dielectric material and the first channel region, and a pure first metal with an n-type work function value conformally deposited in the first opening. The device also includes a second gate structure engaging the second projection adjacent the second channel region. The second gate structure includes a second dielectric material over the second channel region, a second opening over the second dielectric material and the second channel region, and a pure second metal with a p-type work function value conformally deposited in the second opening.
摘要翻译：提供半导体器件。所述装置包括半导体衬底，从衬底向上延伸的第一和第二突起，所述突起在其中具有相应的第一和第二沟道区域，以及与第一沟道区域相邻的第一栅极结构。第一栅极结构包括在第一沟道区上方的第一介电材料，第一介电材料和第一沟道区上的第一开口，以及保形地沉积在第一开口中的具有n型功函数值的纯金属。该装置还包括与邻近第二通道区域的第二突起接合的第二栅极结构。第二栅极结构包括在第二沟道区上方的第二电介质材料，第二电介质材料和第二沟道区上的第二开口，以及保形地沉积在第二开口中的具有p型功函数值的纯的第二金属。

28. 发明授权

US10867789B2 Treatment to control deposition rate 有权
公开(公告)号：US10867789B2
公开(公告)日：2020-12-15
申请号：US16051064
申请日：2018-07-31
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Wan-Yi Kao , Kuang-Yuan Hsu
IPC分类号： H01L21/02 , H01L21/306 , C23C16/02 , H01L21/033 , H01L29/66
CPC分类号： H01L21/02312 , C23C16/02 , H01L21/0217 , H01L21/0228 , H01L21/02123 , H01L21/02211 , H01L21/02274 , H01L21/0332 , H01L21/306 , H01L29/66795
摘要： A treatment, structure and system are provided that modify the deposition process of a material that can occur over two differing materials. In an embodiment the deposition rates may be adjusted by the treatment to change the deposition rate of one of the materials to be more in line with the deposition rate of a second one of the materials. Also, the deposition rates may be modified to be different from each other, to allow for a more selective deposition over the first one of the materials than over the second one of the materials.

29. 发明申请

US20200251567A1 Metal Gate Structure 审中-公开
公开(公告)号：US20200251567A1
公开(公告)日：2020-08-06
申请号：US16856211
申请日：2020-04-23
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Peng-Soon Lim , Da-Yuan Lee , Kuang-Yuan Hsu
IPC分类号： H01L29/423 , H01L21/28 , H01L21/311 , H01L21/285 , H01L21/8234 , H01L29/49
摘要： A method includes forming a trench over a substrate, wherein the trench is surrounded by gate spacers and an inter-layer dielectric layer, depositing a dielectric layer on a bottom and along sidewalls of the trench, depositing a metal layer over the dielectric layer, depositing a protection layer over the metal layer, wherein the protection layer has an uneven thickness, applying an etch-back process to the protection layer and the metal layer, wherein as a result of applying the etch-back process, a portion of the metal layer has been removed and at least a portion of the protection layer remains at the bottom of the trench and removing the protection layer from the trench.

30. 发明授权

US10312075B2 Treatment system and method 有权
公开(公告)号：US10312075B2
公开(公告)日：2019-06-04
申请号：US14989227
申请日：2016-01-06
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Wan-Yi Kao , Kuang-Yuan Hsu , Tze-Liang Lee
IPC分类号： H01L21/00 , H01L21/02 , H01L21/027 , H01L21/3105 , H01L21/311
摘要： A method of descumming a dielectric layer is provided. In an embodiment the dielectric layer is deposited over a substrate, and a photoresist is applied, exposed, and developed after the photoresist has been applied. Once the pattern of the photoresist is transferred to the underlying dielectric layer, a descumming process is performed, wherein the descumming process utilizes a mixture of a carbon-containing precursor, a descumming precursor, and a carrier gas. The mixture is ignited into a treatment plasma, and the treatment plasma is applied to the dielectric layer in order to descum the dielectric layer.

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