专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US08314021B2 Method for fabricating semiconductor device with buried gates 失效
标题翻译：制造具有埋栅的半导体器件的方法
公开(公告)号：US08314021B2
公开(公告)日：2012-11-20
申请号：US12938806
申请日：2010-11-03
申请人： Jik-Ho Cho , Seung-Jin Yeom , Seung-Hee Hong , Nam-Yeal Lee
发明人： Jik-Ho Cho , Seung-Jin Yeom , Seung-Hee Hong , Nam-Yeal Lee
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28088 , C23C16/045 , C23C16/34 , C23C16/45525 , C23C16/56 , H01L29/4236 , H01L29/4966 , H01L29/66621
摘要： A method for fabricating a semiconductor device includes: forming a thin film over trenches by using a first source gas and a first reaction gas; performing a first post-treatment on the thin film by using a second reaction gas; and performing a second post-treatment on the thin film by using a second source gas.
摘要翻译：一种制造半导体器件的方法包括：通过使用第一源气体和第一反应气体在沟槽上形成薄膜; 通过使用第二反应气体对所述薄膜进行第一后处理; 以及通过使用第二源气体对所述薄膜进行第二后处理。

22. 发明授权

US08048758B2 Method for fabricating a capacitor utilizes the sacrificial pattern covering the cell region 失效
标题翻译：用于制造电容器的方法利用覆盖单元区域的牺牲图案
公开(公告)号：US08048758B2
公开(公告)日：2011-11-01
申请号：US13069294
申请日：2011-03-22
申请人： Jae-Sung Roh , Kee-Jeung Lee , Han-Sang Song , Seung-Jin Yeom , Deok-Sin Kil , Young-Dae Kim , Jin-Hyock Kim
发明人： Jae-Sung Roh , Kee-Jeung Lee , Han-Sang Song , Seung-Jin Yeom , Deok-Sin Kil , Young-Dae Kim , Jin-Hyock Kim
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/10852 , H01L28/65
摘要： A method for fabricating a capacitor includes forming an isolation layer over a cell region and a peripheral region of a substrate. The isolation layer forms a plurality of open regions in the cell region. Storage nodes are formed on surfaces of the open regions. A sacrificial pattern is formed over the isolation layer and covers the cell region. The isolation layer is etched in the peripheral region to expose side portions of the resulting structure obtained after forming the sacrificial pattern in the cell region. With the sacrificial pattern supporting the storage nodes, the isolation layer in the cell region is removed. The sacrificial pattern is then removed.
摘要翻译：制造电容器的方法包括在衬底的单元区域和周边区域上形成隔离层。隔离层在单元区域中形成多个开放区域。存储节点形成在开放区域的表面上。在隔离层上形成牺牲图案并覆盖单元区域。在外围区域中蚀刻隔离层，以暴露在单元区域中形成牺牲图案之后获得的所得结构的侧面部分。利用支持存储节点的牺牲图案，移除单元区域中的隔离层。然后去除牺牲图案。

23. 发明申请

US20110027465A1 METHOD FOR FORMING DIELECTRIC FILM AND METHOD FOR FORMING CAPACITOR IN SEMICONDUCTOR DEVICE USING THE SAME 失效
标题翻译：用于形成介电膜的方法和在使用其的半导体器件中形成电容器的方法
公开(公告)号：US20110027465A1
公开(公告)日：2011-02-03
申请号：US12895678
申请日：2010-09-30
申请人： Deok-Sin KIL , Kwon Hong , Seung-Jin Yeom
发明人： Deok-Sin KIL , Kwon Hong , Seung-Jin Yeom
IPC分类号： H01G9/00 , C23C16/40 , H01G9/07
CPC分类号： C23C16/40 , C23C16/45529 , C23C16/45531 , H01L21/02178 , H01L21/02189 , H01L21/02194 , H01L21/0228 , H01L21/3141 , H01L21/31616 , H01L21/31641 , H01L27/10814 , H01L28/40
摘要： Provided is a method for forming a dielectric film in a semiconductor device, wherein the method can improve a dielectric characteristic and a leakage current characteristic. According to specific embodiments of the present invention, the method for forming a dielectric film includes: forming a zirconium dioxide (ZrO2) layer over a wafer in a predetermined thickness that does not allow continuous formation of the ZrO2 layer; and forming an aluminum oxide (Al2O3) layer over portions of the wafer where the ZrO2 layer is not formed, in a predetermined thickness that does not allow continuous formation of the Al2O3 layer.
摘要翻译：提供一种在半导体器件中形成电介质膜的方法，其中该方法可以改善介电特性和漏电流特性。根据本发明的具体实施方案，形成电介质膜的方法包括：在不允许连续形成ZrO 2层的预定厚度的晶片上形成二氧化锆（ZrO 2）层; 并且在没有形成ZrO 2层的晶片的部分上形成氧化铝（Al 2 O 3）层，其厚度不能连续地形成Al 2 O 3层。

24. 发明授权

US07781336B2 Semiconductor device including ruthenium electrode and method for fabricating the same 有权
标题翻译：包括钌电极的半导体器件及其制造方法
公开(公告)号：US07781336B2
公开(公告)日：2010-08-24
申请号：US11978604
申请日：2007-10-30
申请人： Jin-Hyock Kim , Jae-Sung Roh , Seung-Jin Yeom , Kee-Jeung Lee , Han-Sang Song , Deok-Sin Kil , Young-Dae Kim
发明人： Jin-Hyock Kim , Jae-Sung Roh , Seung-Jin Yeom , Kee-Jeung Lee , Han-Sang Song , Deok-Sin Kil , Young-Dae Kim
IPC分类号： H01L21/00
CPC分类号： H01L21/32136 , H01L21/32115 , H01L21/76843 , H01L21/76865 , H01L28/65
摘要： A semiconductor device includes a semiconductor substrate, an insulation pattern on the semiconductor substrate, and an etch stop layer on the insulating pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the substrate, a first plug filled in a portion of the contact hole, a diffusion barrier layer formed above the first plug and in a bottom portion and on sidewalls of a remaining portion of the contact hole, a second plug formed on the diffusion barrier layer and filled in the contact hole, and a storage node coupled to and formed on the second plug.
摘要翻译：半导体器件包括半导体衬底，半导体衬底上的绝缘图案和绝缘图案上的蚀刻停止层，绝缘图案和蚀刻停止层限定暴露衬底的接触孔，第一插头填充在部分在所述第一插头上形成的扩散阻挡层，在所述接触孔的剩余部分的底部和侧壁上形成的扩散阻挡层，形成在所述扩散阻挡层上并填充在所述接触孔中的第二插塞，耦合到并形成在第二插头上的节点。

25. 发明授权

US07772132B2 Method for forming tetragonal zirconium oxide layer and method for fabricating capacitor having the same 失效
标题翻译：形成四方晶氧化锆层的方法及其制造具有该方法的电容器的方法
公开(公告)号：US07772132B2
公开(公告)日：2010-08-10
申请号：US11476789
申请日：2006-06-29
申请人： Deok-Sin Kil , Han-Sang Song , Seung-Jin Yeom , Ki-Seon Park , Jae-Sung Roh , Jin-Hyock Kim
发明人： Deok-Sin Kil , Han-Sang Song , Seung-Jin Yeom , Ki-Seon Park , Jae-Sung Roh , Jin-Hyock Kim
IPC分类号： H01L21/469 , H01L21/31
CPC分类号： H01L21/02189 , C23C16/405 , C23C16/45527 , H01L21/0228 , H01L21/02337 , H01L21/3141 , H01L21/31641 , H01L28/40 , Y02T50/67
摘要： A method for forming a zirconium oxide (ZrO2) layer on a substrate in a chamber includes controlling a temperature of the substrate; and repeating a unit cycle of an atomic layer deposition (ALD) method. The unit cycle includes supplying a zirconium (Zr) source into a chamber, parts of the Zr source being adsorbed into a surface of the substrate; purging non-adsorbed parts of the Zr source remaining inside the chamber; supplying a reaction gas for reacting with the adsorbed parts of the Zr source; and purging non-reacted parts of the reaction gas remaining inside the chamber and reaction byproducts, wherein the temperature of the substrate and a concentration of the reaction gas are controlled such that the ZrO2 layer is formed with a tetragonal structure.
摘要翻译：在室内的基板上形成氧化锆（ZrO 2）层的方法包括：控制基板的温度; 并重复原子层沉积（ALD）方法的单位周期。单元循环包括将锆（Zr）源供应到室中，部分Zr源被吸附到衬底的表面中; 吹扫保留在室内的Zr源的未吸附部分; 供给与Zr源的吸附部反应的反应气体，并且清洗保留在室内的反应气体的未反应部分和反应副产物，其中控制基板的温度和反应气体的浓度使得ZrO 2层形成为四方结构。

26. 发明申请

US20070148897A1 Method for fabricating capacitor in semiconductor device 有权
标题翻译：在半导体器件中制造电容器的方法
公开(公告)号：US20070148897A1
公开(公告)日：2007-06-28
申请号：US11448797
申请日：2006-06-08
申请人： Seung-Jin Yeom , Deok-Sin Kil , Jin-Hyock Kim , Ki-Seon Park , Han-Sang Song , Jae-Sung Roh
发明人： Seung-Jin Yeom , Deok-Sin Kil , Jin-Hyock Kim , Ki-Seon Park , Han-Sang Song , Jae-Sung Roh
IPC分类号： H01L21/20
CPC分类号： H01L28/65 , H01L27/10852 , H01L28/91
摘要： A method for fabricating a capacitor in a semiconductor device is provided. The method includes forming an insulation layer over a substrate; flushing a metal source onto the insulation layer to change a characteristic of a surface of the insulation layer to improve adherence of a metal-based material to the surface of the insulation layer; forming a storage node comprising the metal-based material over the flushed insulation layer; and sequentially forming a dielectric layer and a plate electrode over the metal-based storage node.
摘要翻译：提供了一种在半导体器件中制造电容器的方法。该方法包括在衬底上形成绝缘层; 将金属源冲洗到绝缘层上以改变绝缘层的表面的特性，以改善金属基材料对绝缘层表面的粘附性; 在所述冲洗绝缘层上形成包括所述金属基材料的存储节点; 并且在金属基存储节点上依次形成电介质层和平板电极。

27. 发明申请

US20070051998A1 Semiconductor memory device with dielectric structure and method for fabricating the same 审中-公开
标题翻译：具有介质结构的半导体存储器件及其制造方法
公开(公告)号：US20070051998A1
公开(公告)日：2007-03-08
申请号：US11387563
申请日：2006-03-22
申请人： Deok-Sin Kil , Kwon Hong , Seung-Jin Yeom
发明人： Deok-Sin Kil , Kwon Hong , Seung-Jin Yeom
IPC分类号： H01L29/94
CPC分类号： H01L29/7881 , H01L29/40114 , H01L29/513
摘要： A semiconductor memory device with a dielectric structure and a method for fabricating the same are provided. The dielectric structure includes: a first dielectric layer having a dielectric constant of approximately 25 or higher; a second dielectric layer including a material having a crystallization rate lower than the first dielectric layer and formed over the first dielectric layer; and a third dielectric layer including a material substantially identical to that of the first dielectric layer and formed over the second dielectric layer.
摘要翻译：提供具有介电结构的半导体存储器件及其制造方法。电介质结构包括：介电常数约为25或更高的第一介电层; 第二电介质层，其包括具有比所述第一电介质层低的结晶化率的材料，并形成在所述第一介电层上; 以及第三电介质层，其包括与所述第一电介质层的材料基本相同的材料，并形成在所述第二电介质层上。

28. 发明授权

US07045071B2 Method for fabricating ferroelectric random access memory device 失效
标题翻译：制造铁电随机存取存储器件的方法
公开(公告)号：US07045071B2
公开(公告)日：2006-05-16
申请号：US10739434
申请日：2003-12-17
申请人： Soon-Yong Kweon , Seung-Jin Yeom
发明人： Soon-Yong Kweon , Seung-Jin Yeom
IPC分类号： H01B13/00 , H01L21/00
CPC分类号： H01L21/76846 , H01L21/02052 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L21/7687 , H01L21/76877 , H01L21/76889 , H01L28/55 , H01L28/65
摘要： The present invention relates to a method for fabricating a ferroelectric random access memory device. The method includes the steps of: (a) forming a first inter-layer insulation layer on a substrate providing a transistor; (b) etching the first inter-layer insulation layer to form a storage node contact hole exposing a partial portion of the substrate; (c) burying a storage node contact including a plug and a barrier metal layer into the storage node contact hole; (d) forming an adhesion layer on the storage node contact and the first inter-layer insulation layer; (e) inducing a predetermined portion of the adhesion layer to be cracked, the predetermined portion disposed above an upper part of the plug; (f) selectively removing the cracked predetermined portion to expose a surface of the barrier metal layer formed on the plug; and (g) forming a ferroelectric capacitor connected to the plug through the exposed surface of the barrier metal layer.
摘要翻译：本发明涉及一种制造铁电随机存取存储器件的方法。该方法包括以下步骤：（a）在提供晶体管的衬底上形成第一层间绝缘层; （b）蚀刻第一层间绝缘层以形成暴露衬底的部分部分的存储节点接触孔; （c）将包括塞子和阻挡金属层的存储节点接触件埋入存储节点接触孔中; （d）在所述储存节点接触件和所述第一层间绝缘层上形成粘合层; （e）引起所述粘合层的预定部分被破裂，所述预定部分设置在所述插头的上部上方; （f）选择性地去除裂纹的预定部分以暴露形成在插塞上的阻挡金属层的表面; 和（g）通过阻挡金属层的暴露表面形成连接到插塞的铁电电容器。

29. 发明申请

US20050205912A1 Ferroelectric memory device with merged-top-plate structure and method for fabricating the same 失效
标题翻译：具有合并顶板结构的铁电存储器件及其制造方法
公开(公告)号：US20050205912A1
公开(公告)日：2005-09-22
申请号：US11135767
申请日：2005-05-23
申请人： Eun-Seok Choi , Seung-Jin Yeom
发明人： Eun-Seok Choi , Seung-Jin Yeom
IPC分类号： H01L21/8242 , H01L21/02 , H01L21/8246 , H01L27/115 , H01L29/76 , H01L21/00 , H01L29/94
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/57 , H01L28/60 , H01L28/65 , H01L28/75
摘要： The inventive ferroelectric memory device includes: a semiconductor substrate providing elements of a transistor; a first inter-layer insulating layer formed on the semiconductor substrate; a storage node contact connected to elements of the transistor by passing through the first inter-layer insulating layer; a barrier layer contacting simultaneously to the storage node contact and the first inter-layer insulating layer; a lower electrode having a space for isolating the first inter-layer insulating layer and being formed on the barrier layer; a glue layer being formed on the first inter-layer insulating layer and encompassing lateral sides of the lower electrode as filling the space; a second inter-layer insulating layer exposing a surface of the lower electrode and encompassing the glue layer; a ferroelectric layer formed on the glue layer including the second inter-layer insulating layer; and an upper electrode formed on the ferroelectric layer.
摘要翻译：本发明的铁电存储器件包括：提供晶体管元件的半导体衬底; 形成在所述半导体基板上的第一层间绝缘层; 通过穿过所述第一层间绝缘层而连接到所述晶体管的元件的存储节点接触; 与所述存储节点接触部和所述第一层间绝缘层同时接触的阻挡层; 具有用于隔离所述第一层间绝缘层并形成在所述阻挡层上的空间的下电极; 胶层在第一层间绝缘层上形成，并且在下部电极的横向侧面填充空间; 第二层间绝缘层，暴露下电极的表面并包围胶层; 形成在包括第二层间绝缘层的胶层上的铁电层; 以及形成在强电介质层上的上电极。

30. 发明申请

US20050098812A1 Semiconductor device having a capacitor and method for the manufacture thereof 审中-公开
标题翻译：具有电容器的半导体器件及其制造方法
公开(公告)号：US20050098812A1
公开(公告)日：2005-05-12
申请号：US10632956
申请日：2003-08-04
申请人： Woo-Seok Yang , Seung-Jin Yeom , Yong-Sik Yu
发明人： Woo-Seok Yang , Seung-Jin Yeom , Yong-Sik Yu
IPC分类号： C23C16/40 , H01L21/02 , H01L21/314 , H01L21/316 , H01L21/768 , H01L21/8242 , H01L21/8246 , H01L23/522 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L21/0228 , H01L21/02164 , H01L21/02178 , H01L21/02211 , H01L21/3141 , H01L21/31616 , H01L21/76832 , H01L21/76834 , H01L21/76895 , H01L27/1085 , H01L28/40
摘要： A semiconductor device for use in a memory cell includes an active matrix provided with a silicon substrate, a transistor formed on the silicon substrate, a capacitor structure formed over the transistor, a metal interconnection for electrically connecting the capacitor structure to the transistor, a barrier layer formed on top of the metal interconnection and an inter-metal dielectric (IMD) layer formed on top of the barrier layer, wherein the barrier layer is made of a material such as Al2O3 or the like. The IMD layer is formed by using a plasma chemical vapor deposition (CVD) in a hydrogen rich atmosphere, wherein the barrier layer is used for preventing the capacitor structure from the hydrogen.
摘要翻译：用于存储单元的半导体器件包括：设置有硅衬底的有源矩阵，形成在硅衬底上的晶体管，形成在晶体管上的电容器结构，用于将电容器结构电连接到晶体管的金属互连，形成在金属互连的顶部上的层，以及形成在阻挡层顶部上的金属间电介质（IMD）层，其中阻挡层由诸如Al 2 O 3的材料制成， 3等。通过在富氢气氛中使用等离子体化学气相沉积（CVD）形成IMD层，其中阻挡层用于防止电容器结构脱离氢。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式