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21. 发明申请

US20100241784A1 System and method for storing data in a virtualized high speed memory system 有权
标题翻译：在虚拟化高速存储器系统中存储数据的系统和方法
公开(公告)号：US20100241784A1
公开(公告)日：2010-09-23
申请号：US12584645
申请日：2009-09-08
申请人： Sundar Iyer , Shang-Tse Chuang
发明人： Sundar Iyer , Shang-Tse Chuang
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/0292 , G06F12/06 , G06F12/0607 , G06F12/10 , G06F12/1009 , G06F2212/1024 , G06F2212/152 , G06F2212/502 , G06F2212/657
摘要： A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict.
摘要翻译：公开了一种用于提供高速存储器操作的系统和方法。该技术使用虚拟化的存储器空间将虚拟地址空间映射到更大的物理地址空间，其中不会发生存储体冲突。更大的物理地址空间用于通过将正在写入存储器的数据的虚拟存储器地址移动到物理存储器中的不同位置来消除存储器组冲突而发生存储器组冲突。

22. 发明申请

US20060123139A1 Intelligent memory interface 有权
标题翻译：智能记忆体接口
公开(公告)号：US20060123139A1
公开(公告)日：2006-06-08
申请号：US11222387
申请日：2005-09-07
申请人： Sundar Iyer , Nick McKeown , Morgan Littlewood
发明人： Sundar Iyer , Nick McKeown , Morgan Littlewood
IPC分类号： G06F3/00
CPC分类号： G06F1/3209 , H04L49/3009 , H04L49/3036 , H04L49/90
摘要： The present invention introduces various high-level memory interfaces for interfacing with an intelligent memory system. The memory interfaces may be hardware-based or software-based. In one embodiment, two layers of interfaces are implemented such that an internal interface may evolve over successive generations without affecting an externally visible interface.
摘要翻译：本发明引入了用于与智能存储器系统接口的各种高级存储器接口。存储器接口可以是基于硬件的或基于软件的。在一个实施例中，实现两层接口，使得内部接口可以在连续世代上演进而不影响外部可见接口。

23. 发明授权

US07043494B1 Fast, deterministic exact match look-ups in large tables 失效
标题翻译：快速，确定性的大型表格中的精确匹配查找
公开(公告)号：US07043494B1
公开(公告)日：2006-05-09
申请号：US10353723
申请日：2003-01-28
申请人： Deepali Joshi , Ajit Shelat , Amit Phansalkar , Sundar Iyer , Ramana Kompella , George Varghese
发明人： Deepali Joshi , Ajit Shelat , Amit Phansalkar , Sundar Iyer , Ramana Kompella , George Varghese
IPC分类号： G06F17/30
CPC分类号： G06F17/30961 , Y10S707/99942 , Y10S707/99943 , Y10S707/99944 , Y10S707/99945
摘要： A combined hash table/bucket trie technique facilitates fast, deterministic, memory-efficient exact match look-ups on extremely large tables. A limited number of hash keys which collide on the same location can be stored in the hash table. If further keys collide on the same location, a bucket trie is formed, the colliding keys are stored in the trie, and trie traversal information is stored in the hash table. Regardless of the number of buckets in the trie, an input key need only be compared with the keys in one bucket to detect a stored key identical to the input key or conclude that no stored key is identical to the input key.
摘要翻译：组合的哈希表/桶特技技术有助于在极大的表上快速，确定性，内存高效的精确匹配查找。在相同位置上碰撞的有限数量的散列键可以存储在散列表中。如果其他键在相同的位置相冲突，则形成桶形特技，将碰撞键存储在木偶中，并将特里斯遍历信息存储在散列表中。不管行李中的桶数如何，输入密钥只需要与一个桶中的密钥进行比较，以检测与输入密钥相同的存储密钥，或者得出结论：没有存储密钥与输入密钥相同。

24. 发明申请

US20050225375A1 CIRCUITS ASSOCIATED WITH FUSIBLE ELEMENTS FOR ESTABLISHING AND DETECTING OF THE STATES OF THOSE ELEMENTS 失效
标题翻译：与建立和检测元素状态的可信元素相关联的电路
公开(公告)号：US20050225375A1
公开(公告)日：2005-10-13
申请号：US10820092
申请日：2004-04-07
申请人： Mark Anderson , Sundar Iyer , Chandrasekara Kothandaraman , Edward Maciejewski , George Smith
发明人： Mark Anderson , Sundar Iyer , Chandrasekara Kothandaraman , Edward Maciejewski , George Smith
IPC分类号： G11C17/16 , G11C17/18 , H01H37/76
CPC分类号： G11C17/16 , G11C17/18
摘要： An identification circuit for establishing and sensing the state of a fusible element used in on chip identification of the chip's type comprising: a circuit establishing control signals for turning the identification circuit on and off; dual paths energized by the control signals generated by the level setting circuit to energize one path through the fusible element to provide a state level and the other path through a reference path which provides a reference voltage level which is distinguishable from both the blown and unblown states of the fusible element; a differential sensing circuit for comparing the reference voltage level to the state level to provide a signal indicating the state of the fusible element; and protection circuitry to protect the circuit during an operation in which the state of the fusible element is set.
摘要翻译：一种识别电路，用于建立和感测用于芯片类型片上识别的可熔元件的状态，包括：建立用于打开和关闭识别电路的控制信号的电路; 通过由电平设置电路产生的控制信号激励的双路径，以激励通过可熔元件的一条路径，以提供状态电平，并且通过参考路径的另一条路径，该参考路径提供可与吹制状态和非吹出状态区分的参考电压电平的易熔元素; 差分感测电路，用于将参考电压电平与状态电平进行比较，以提供指示可熔元件的状态的信号; 以及用于在设置可熔元件的状态的操作期间保护电路的保护电路。

25. 发明授权

US06691168B1 Method and apparatus for high-speed network rule processing 有权
标题翻译：用于高速网络规则处理的方法和装置
公开(公告)号：US06691168B1
公开(公告)日：2004-02-10
申请号：US09246572
申请日：1999-02-08
申请人： Subhash Bal , Raghunath Iyer , Sundar Iyer , Ramana Rao
发明人： Subhash Bal , Raghunath Iyer , Sundar Iyer , Ramana Rao
IPC分类号： G06F15173
CPC分类号： H04L63/0263 , H04L29/06 , H04L29/12009 , H04L49/205 , H04L49/25 , H04L49/50 , H04L61/00 , H04L63/0227 , H04L63/1416 , H04L69/16 , H04L69/161 , H04L69/163 , H04L69/22
摘要： As Internet packet flow increases, the demand for high speed packet filtering has grown. The present invention introduces several methods for a high-speed rule processing. The methods are geared towards Internet Protocol (IP) packet processing.
摘要翻译：随着互联网分组流量的增加，对高速分组过滤的需求也在增长。本发明引入了用于高速规则处理的几种方法。这些方法面向互联网协议（IP）数据包处理。

26. 再颁专利

USRE45097E1 High speed memory and input/output processor subsystem for efficiently allocating and using high-speed memory and slower-speed memory 有权
标题翻译：高速存储器和输入/输出处理器子系统，用于高效分配和使用高速存储器和较慢速度的存储器
公开(公告)号：USRE45097E1
公开(公告)日：2014-08-26
申请号：US13365136
申请日：2012-02-02
申请人： Sundar Iyer , Nick McKeown
发明人： Sundar Iyer , Nick McKeown
IPC分类号： G06F13/00
CPC分类号： G06F13/1668 , G06F12/0223 , G06F12/0607 , G06F2212/205
摘要： An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive part that is then handled by the input/output processor. An input/output processor is designed by analyzing common input/output and memory access patterns and implementing methods tailored to efficiently handle those commonly occurring patterns. One technique that an input/output processor may use is to divide memory tasks into high frequency or high-availability components and low frequency or low-availability components. After dividing a memory task in such a manner, the input/output processor then uses high-speed memory (such as SRAM) to store the high frequency and high-availability components and a slower-speed memory (such as commodity DRAM) to store the low frequency and low-availability components. Another technique used by the input/output processor is to allocate memory in such a manner that all memory bank conflicts are eliminated. By eliminating any possible memory bank conflicts, the maximum random access performance of DRAM memory technology can be achieved.
摘要翻译：提出了一种用于加速处理器的输入/输出和存储器访问操作的输入/输出处理器。输入/输出处理器的关键思想是将输入/输出和存储器访问操作任务功能划分为由处理器处理的计算密集型部分以及I / O或存储器密集部分，然后由输入/输出处理处理器。输入/输出处理器是通过分析常用的输入/输出和存储器访问模式来设计的，并且实现了有效处理这些常见模式的方法。输入/输出处理器可以使用的一种技术是将存储器任务分为高频或高可用性组件以及低频或低可用性组件。在以这种方式分配存储器任务之后，输入/输出处理器然后使用高速存储器（例如SRAM）来存储高频和高可用性组件以及较慢速存储器（例如商品DRAM）来存储低频和低可用性组件。输入/输出处理器使用的另一技术是以消除所有存储器组冲突的方式分配存储器。通过消除任何可能的存储体冲突，可以实现DRAM存储器技术的最大随机存取性能。

27. 发明授权

US07362703B1 Method for deflection routing of data packets to alleviate link overload in IP networks 有权
标题翻译：数据包的偏转路由方法，以减轻IP网络中的链路过载
公开(公告)号：US07362703B1
公开(公告)日：2008-04-22
申请号：US10616793
申请日：2003-07-10
申请人： Nina Taft , Supratik Bhattacharyya , Christophe Diot , Sundar Iyer
发明人： Nina Taft , Supratik Bhattacharyya , Christophe Diot , Sundar Iyer
IPC分类号： H04L12/26 , G06F15/173
CPC分类号： H04L45/12 , H04L45/06
摘要： The present invention provides methods for deflecting the routing data packets in an IP network to avoid overloaded links and to alleviate link congestion. One method in accordance with the present invention is, when the next link on the shortest route path is congested, to deflect a data packet to an adjacent node with a decreasing cost to the destination that is not the next hop on the shortest route path to the destination. A further method in accordance with the present invention deflects a data packet to an intra-PoP node with a small increase in cost to the destination to avoid a congested link. These and other methods in accordance with the present invention may be used alone or in combination as a method for deflection routing data packets to alleviate and avoid link congestion in an IP network.
摘要翻译：本发明提供了在IP网络中偏转路由数据分组以避免重载链路并减轻链路拥塞的方法。根据本发明的一种方法是当最短路径路径上的下一条链路拥塞时，将数据分组以相对于不是下一跳的目的地的成本降低到最短路由路径上的相邻节点目的地。根据本发明的另一种方法是将数据分组偏移到PoP节点内，以较少的成本增加到目的地以避免拥塞的链路。根据本发明的这些和其他方法可以单独使用或组合使用作为偏转路由数据分组的方法，以减轻和避免IP网络中的链路拥塞。

28. 发明授权

US06631466B1 Parallel string pattern searches in respective ones of array of nanocomputers 有权
标题翻译：并行字符串模式搜索纳米计算机阵列的各个
公开(公告)号：US06631466B1
公开(公告)日：2003-10-07
申请号：US09569593
申请日：2000-05-09
申请人： Vikram Chopra , Ajay Desai , Raghunath Iyer , Sundar Iyer , Moti Jiandani , Ajit Shelat , Navneet Yadav
发明人： Vikram Chopra , Ajay Desai , Raghunath Iyer , Sundar Iyer , Moti Jiandani , Ajit Shelat , Navneet Yadav
IPC分类号： G06F706
CPC分类号： H04L29/06 , H04L29/12009 , H04L49/205 , H04L49/25 , H04L49/3009 , H04L49/355 , H04L49/50 , H04L61/00 , H04L63/0227 , H04L63/0263 , H04L63/1416 , H04L69/16 , H04L69/161 , H04L69/163 , H04L69/22 , Y10S707/99936
摘要： A high-speed parallel pattern searching system is disclosed. The high-speed parallel pattern searching system allows the body of a data packet to be searched for one or more patterns such as a string or a series of strings. These string patterns can be defined by the grammar of regular expressions. In the invention, one or more patterns are loaded into one or more nanocomputers that operate in parallel. A control system then feeds a packet body into the participating nanocomputers such that each participating nanocomputer tests for a match. The various tests performed by the nanocomputers may be combined to perform complex searches. These nanocomputer searches are performed in parallel. Furthermore, several different searches may be combined together using control statements. A combination of these searches engines can be supported such that data is also looked at in parallel.
摘要翻译：公开了一种高速并行模式搜索系统。高速并行模式搜索系统允许搜索数据分组的主体一个或多个模式，例如字符串或一系列字符串。这些字符串模式可以通过正则表达式的语法来定义。在本发明中，一个或多个图案被加载到并行操作的一个或多个纳米计算机中。然后，控制系统将分组主体馈送到参与的纳米计算机中，使得每个参与的纳米计算机测试匹配。可以组合由纳米计算机执行的各种测试以执行复杂的搜索。这些纳米计算机搜索是并行执行的。此外，几个不同的搜索可以使用控制语句组合在一起。可以支持这些搜索引擎的组合，使得还并行地查看数据。

29. 发明授权

US09274586B2 Intelligent memory interface 有权
标题翻译：智能记忆体接口
公开(公告)号：US09274586B2
公开(公告)日：2016-03-01
申请号：US11222387
申请日：2005-09-07
申请人： Sundar Iyer , Nick McKeown , Morgan Littlewood
发明人： Sundar Iyer , Nick McKeown , Morgan Littlewood
IPC分类号： G06F12/00 , G06F1/32 , H04L12/861 , H04L12/935
CPC分类号： G06F1/3209 , H04L49/3009 , H04L49/3036 , H04L49/90
摘要： Many computer processing tasks require large numbers of memory intensive operations to be performed very rapidly. For example, computer network requires that packets be placed into and removed from First-In First-Out (FIFO) queues, numerous counters to be maintained and routing table look-ups to be performed. All of these operations must be performed at very high-speeds in order to keep up with today's high-speed computer network traffic. To help perform these high-speed memory tasks, a high-speed intelligent memory subsystem has been developed. The high-speed intelligent memory subsystem handles the intricacies of these memory operations such that a main process is relieved of some of its duties. Various different high-level memory interfaces for interfacing with the intelligent memory subsystem. The memory interfaces may be hardware-based or software-based. In one embodiment, two layers of interfaces are implemented such that an internal interface may evolve over successive generations without affecting an externally visible interface.
摘要翻译：许多计算机处理任务需要非常快速地执行大量的内存密集型操作。例如，计算机网络要求将数据包放入先入先出（FIFO）队列中的数据包，要保留的许多计数器和要执行的路由表查找。所有这些操作必须以非常高的速度执行，以便跟上当今的高速计算机网络流量。为了帮助执行这些高速存储器任务，开发了高速智能存储器子系统。高速智能存储器子系统处理这些记忆操作的复杂性，使得主程序免除了其一些职责。各种不同的高级存储器接口，用于与智能存储器子系统进行接口。存储器接口可以是基于硬件的或基于软件的。在一个实施例中，实现两层接口，使得内部接口可以在连续世代上演进而不影响外部可见接口。

30. 发明授权

US07657706B2 High speed memory and input/output processor subsystem for efficiently allocating and using high-speed memory and slower-speed memory 有权
标题翻译：高速存储器和输入/输出处理器子系统，用于高效分配和使用高速存储器和较慢速度的存储器
公开(公告)号：US07657706B2
公开(公告)日：2010-02-02
申请号：US11016572
申请日：2004-12-17
申请人： Sundar Iyer , Nick McKeown
发明人： Sundar Iyer , Nick McKeown
IPC分类号： G06F13/00
CPC分类号： G06F13/1668 , G06F12/0223 , G06F12/0607 , G06F2212/205
摘要： An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive part that is then handled by the input/output processor. An input/output processor is designed by analyzing common input/output and memory access patterns and implementing methods tailored to efficiently handle those commonly occurring patterns. One technique that an input/output processor may use is to divide memory tasks into high frequency or high-availability components and low frequency or low-availability components. After dividing a memory task in such a manner, the input/output processor then uses high-speed memory (such as SRAM) to store the high frequency and high-availability components and a slower-speed memory (such as commodity DRAM) to store the low frequency and low-availability components. Another technique used by the input/output processor is to allocate memory in such a manner that all memory bank conflicts are eliminated. By eliminating any possible memory bank conflicts, the maximum random access performance of DRAM memory technology can be achieved.
摘要翻译：提出了一种用于加速处理器的输入/输出和存储器访问操作的输入/输出处理器。输入/输出处理器的关键思想是将输入/输出和存储器访问操作任务功能划分为由处理器处理的计算密集型部分以及I / O或存储器密集部分，然后由输入/输出处理处理器。输入/输出处理器是通过分析常用的输入/输出和存储器访问模式来设计的，并且实现了有效处理这些常见模式的方法。输入/输出处理器可以使用的一种技术是将存储器任务分为高频或高可用性组件以及低频或低可用性组件。在以这种方式分配存储器任务之后，输入/输出处理器然后使用高速存储器（例如SRAM）来存储高频和高可用性组件以及较慢速存储器（例如商品DRAM）来存储低频和低可用性组件。输入/输出处理器使用的另一技术是以消除所有存储器组冲突的方式分配存储器。通过消除任何可能的存储体冲突，可以实现DRAM存储器技术的最大随机存取性能。

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