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21. 发明申请

US20090095984A1 DIELECTRIC INTERFACE FOR GROUP III-V SEMICONDUCTOR DEVICE 有权
标题翻译： III-V族半导体器件的介电接口
公开(公告)号：US20090095984A1
公开(公告)日：2009-04-16
申请号：US12338839
申请日：2008-12-18
申请人： Justin K. Brask , Suman Datta , Mark L. Doczy , James M. Blackwell , Matthew V. Metz , Jack T. Kavalieros , Robert S. Chau
发明人： Justin K. Brask , Suman Datta , Mark L. Doczy , James M. Blackwell , Matthew V. Metz , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/28 , H01L29/20
CPC分类号： H01L21/314 , H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/28008 , H01L21/3141 , H01L21/31616 , H01L21/31645 , H01L29/2003 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/66462 , H01L29/7784
摘要： A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.
摘要翻译：描述了III-V族半导体器件及其制造方法。高k电介质通过硫族化物区域连接到约束区域。

22. 发明授权

US07425500B2 Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors 有权
标题翻译：在三维晶体管的外延生长的源极和漏极区上的均匀的硅化物金属
公开(公告)号：US07425500B2
公开(公告)日：2008-09-16
申请号：US11395940
申请日：2006-03-31
申请人： Matthew V. Metz , Suman Datta , Mark L. Doczy , Jack T. Kavalieros , Justin K. Brask , Robert S. Chau
发明人： Matthew V. Metz , Suman Datta , Mark L. Doczy , Jack T. Kavalieros , Justin K. Brask , Robert S. Chau
IPC分类号： H01L21/44
CPC分类号： H01L21/8234 , H01L21/28518 , H01L21/28562 , H01L29/66545 , H01L29/66628 , H01L29/66795 , H01L29/7851
摘要： A method for fabricating a three-dimensional transistor is described. Atomic Layer Deposition of nickel, in one embodiment, is used to form a uniform silicide on all epitaxially grown source and drain regions, including those facing downwardly.
摘要翻译：对三维晶体管的制造方法进行说明。原子层在一个实施方案中，镍的沉积用于在所有外延生长的源极和漏极区域上形成均匀的硅化物，包括面向下的源极和漏极区域。

23. 发明申请

US20160308014A1 FABRICATION OF CHANNEL WRAPAROUND GATE STRUCTURE FOR FIELD-EFFECT TRANSISTOR 审中-公开
标题翻译：用于场效应晶体管的通道封口结构的制造
公开(公告)号：US20160308014A1
公开(公告)日：2016-10-20
申请号：US15197563
申请日：2016-06-29
申请人： Marko Radosavljevic , Amlan Majumdar , Suman Datta , Jack T. Kavalieros , Brian S. Doyle , Justin K. Brask , Robert S. Chau
发明人： Marko Radosavljevic , Amlan Majumdar , Suman Datta , Jack T. Kavalieros , Brian S. Doyle , Justin K. Brask , Robert S. Chau
IPC分类号： H01L29/423 , H01L29/66 , H01L29/06 , H01L29/786
CPC分类号： H01L29/42392 , H01L21/28079 , H01L21/28194 , H01L29/0673 , H01L29/41775 , H01L29/495 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6656 , H01L29/66606 , H01L29/66636 , H01L29/66742 , H01L29/7834 , H01L29/78618 , H01L29/78696 , Y10S438/926 , Y10S438/957
摘要： A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.
摘要翻译：描述了一种制造具有完全围绕通道区域的栅极的场效应晶体管的方法。离子注入用于使晶体管的沟道区下方的氧化物更易蚀刻，从而允许氧化物在沟道区下方被去除。一旦氧化物在通道区域下方被去除，原子层沉积被用于在通道区域的整个周围形成栅极电介质和金属栅极。

24. 发明授权

US09337307B2 Method for fabricating transistor with thinned channel 有权
公开(公告)号：US09337307B2
公开(公告)日：2016-05-10
申请号：US12949696
申请日：2010-11-18
申请人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
发明人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
IPC分类号： H01L29/66 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/4236 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/66636 , H01L29/66818 , H01L29/7834 , H01L29/7838 , H01L29/785 , H04B1/3827 , Y10S438/926
摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

25. 发明申请

US20110062520A1 METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL 审中-公开
标题翻译：用于制造具有薄型通道的晶体管的方法
公开(公告)号：US20110062520A1
公开(公告)日：2011-03-17
申请号：US12949696
申请日：2010-11-18
申请人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
发明人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
IPC分类号： H01L29/786
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/4236 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/66636 , H01L29/66818 , H01L29/7834 , H01L29/7838 , H01L29/785 , H04B1/3827 , Y10S438/926
摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
摘要翻译：描述了制造具有减薄沟道区的MOS晶体管的方法。在去除虚拟栅极之后蚀刻沟道区。源极和漏极区域具有相对较低的电阻。

26. 发明申请

US20100248209A1 Three-dimensional integrated circuit for analyte detection 审中-公开
标题翻译：用于分析物检测的三维集成电路
公开(公告)号：US20100248209A1
公开(公告)日：2010-09-30
申请号：US11478335
申请日：2006-06-30
申请人： Suman Datta , Shriram Ramanathan , Jack T. Kavalieros , Justin K. Brask , Brandon Barnett
发明人： Suman Datta , Shriram Ramanathan , Jack T. Kavalieros , Justin K. Brask , Brandon Barnett
IPC分类号： G01R27/28 , H01L29/78 , H01L29/66 , H01L21/28 , G01N27/00 , C12Q1/70 , C12Q1/02 , G01N33/92 , G01N33/00 , G01N33/53 , G01N33/68
CPC分类号： G01N27/4145 , G01N27/4146 , Y10T436/143333
摘要： The embodiments of the invention relate to a device having a first substrate comprising a transistor; a second substrate; an insulating layer in between and adjoining the first and second substrates; and an opening within the second substrate, the opening being aligned with the transistor; wherein the transistor is configured to detect an electrical charge change within the opening. Other embodiments relate to a method including providing a substrate comprising a first part, a second part, and an insulating layer in between and adjoining the first and second parts; fabricating a transistor on the first part; and fabricating an opening within the second part, the opening being aligned with the transistor; wherein the transistor is configured to detect an electrical charge change within the opening.
摘要翻译：本发明的实施例涉及具有包括晶体管的第一衬底的器件; 第二基板; 位于第一和第二基板之间并邻接第一和第二基板的绝缘层; 以及在所述第二基板内的开口，所述开口与所述晶体管对准; 其中所述晶体管被配置为检测所述开口内的电荷变化。其他实施例涉及一种方法，包括提供在第一和第二部分之间并与之相邻的第一部分，第二部分和绝缘层的基底; 在第一部分制造晶体管; 以及在所述第二部分内制造开口，所述开口与所述晶体管对准; 其中所述晶体管被配置为检测所述开口内的电荷变化。

27. 发明授权

US07525160B2 Multigate device with recessed strain regions 有权
标题翻译：具有凹陷应变区的多组装置
公开(公告)号：US07525160B2
公开(公告)日：2009-04-28
申请号：US11320309
申请日：2005-12-27
申请人： Jack T. Kavalieros , Justin K. Brask , Suman Datta , Brian S. Doyle , Robert S. Chau
发明人： Jack T. Kavalieros , Justin K. Brask , Suman Datta , Brian S. Doyle , Robert S. Chau
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/66795 , H01L29/7848
摘要： Embodiments of the invention provide a device with a multiple gates. Stress material within recesses of a device body metal gate may cause a stress in channel regions of the device, thereby improving performance of the device.
摘要翻译：本发明的实施例提供具有多个门的装置。器件金属门的凹槽内的应力材料可能在器件的沟道区域中引起应力，从而提高器件的性能。

28. 发明授权

US07485503B2 Dielectric interface for group III-V semiconductor device 有权
标题翻译： III-V族半导体器件的介质界面
公开(公告)号：US07485503B2
公开(公告)日：2009-02-03
申请号：US11292399
申请日：2005-11-30
申请人： Justin K. Brask , Suman Datta , Mark L. Doczy , James M. Blackwell , Matthew V. Metz , Jack T. Kavalieros , Robert S. Chau
发明人： Justin K. Brask , Suman Datta , Mark L. Doczy , James M. Blackwell , Matthew V. Metz , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/335 , H01L21/338 , H01L27/108
CPC分类号： H01L21/314 , H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/28008 , H01L21/3141 , H01L21/31616 , H01L21/31645 , H01L29/2003 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/66462 , H01L29/7784
摘要： A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.
摘要翻译：描述了III-V族半导体器件及其制造方法。高k电介质通过硫族化物区域连接到约束区域。

29. 发明授权

US07402856B2 Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same 有权
标题翻译：具有隔离元件以减轻边缘效应的非平面微电子器件及其制造方法
公开(公告)号：US07402856B2
公开(公告)日：2008-07-22
申请号：US11299102
申请日：2005-12-09
申请人： Justin K. Brask , Jack T. Kavalieros , Brian S. Doyle , Robert S. Chau
发明人： Justin K. Brask , Jack T. Kavalieros , Brian S. Doyle , Robert S. Chau
IPC分类号： H01L29/94
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A non-planar microelectronic device, a method of fabricating the device, and a system including the device. The non-planar microelectronic device comprises: a substrate body including a substrate base and a fin, the fin defining a device portion at a top region thereof; a gate dielectric layer extending at a predetermined height on two laterally opposing sidewalls of the fin, the predetermined height corresponding to a height of the device portion; a device isolation layer on the substrate body and having a thickness up to a lower limit of the device portion; a gate electrode on the device isolation layer and further extending on the gate dielectric layer; an isolation element extending on the two laterally opposing sidewalls of the fin up to a lower limit of the gate dielectric layer, the isolation element being adapted to reduce any fringe capacitance between the gate electrode and regions of the fin extending below the device portion.
摘要翻译：非平面微电子器件，制造器件的方法以及包括该器件的系统。所述非平面微电子器件包括：衬底主体，其包括衬底基座和鳍片，所述鳍片限定其顶部区域处的器件部分; 栅极电介质层，其在所述鳍片的两个横向相对的侧壁上以预定高度延伸，所述预定高度对应于所述器件部分的高度; 在所述衬底主体上的器件隔离层，并且具有至所述器件部分的下限的厚度; 器件隔离层上的栅电极，并进一步在栅介质层上延伸; 隔离元件，其在所述鳍片的两个横向相对的侧壁上延伸到所述栅极电介质层的下限，所述隔离元件适于减小所述栅电极与所述鳍片延伸到所述器件部分下方的区域之间的任何条纹电容。

30. 发明授权

US06953719B2 Integrating n-type and p-type metal gate transistors 有权
公开(公告)号：US06953719B2
公开(公告)日：2005-10-11
申请号：US10851360
申请日：2004-05-20
申请人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
发明人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
IPC分类号： H01L21/3213 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/78 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66545 , H01L21/32134 , H01L21/32137 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/7833 , Y10S438/926
摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

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