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21. 发明申请

US20130207270A1 DUAL-METAL SELF-ALIGNED WIRES AND VIAS 有权
标题翻译：双金属自对准线和VIAS
公开(公告)号：US20130207270A1
公开(公告)日：2013-08-15
申请号：US13371493
申请日：2012-02-13
申请人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/768 , H01L23/49
CPC分类号： H01L23/485 , H01L21/76885 , H01L21/76897 , H01L23/5283 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features.
摘要翻译：形成半导体结构的方法，包括在半导体衬底上形成第一导电间隔物; 相对于所述第一导电间隔物形成第二导电间隔物，所述第二导电间隔物中的至少一个与所述第一导电间隔物中的每一个相邻并与之接触以形成组合的导电间隔物; 相对于第一导电间隔物使第二导电间隔物凹陷，使得第一导电间隔物延伸超过第二导电间隔物; 沉积ILD以覆盖除了第一导电间隔物的暴露边缘之外的第一和第二间隔物; 图案化第一导电间隔物的暴露边缘以将预定位置中的第一导电间隔物的边缘凹入以形成相对于ILD的凹部; 并用绝缘材料填充凹槽，以将第一导电间隔物的未加工的边缘作为过孔留下以后的布线特征。

22. 发明授权

US08482132B2 Pad bonding employing a self-aligned plated liner for adhesion enhancement 有权
公开(公告)号：US08482132B2
公开(公告)日：2013-07-09
申请号：US12575980
申请日：2009-10-08
申请人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/80 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/82 , H01L24/92 , H01L25/50 , H01L2224/05007 , H01L2224/05014 , H01L2224/0502 , H01L2224/05099 , H01L2224/05547 , H01L2224/05554 , H01L2224/0556 , H01L2224/05599 , H01L2224/08121 , H01L2224/80001 , H01L2224/80345 , H01L2224/80357 , H01L2224/80359 , H01L2224/80895 , H01L2224/80896 , H01L2224/821 , H01L2224/9212 , H01L2225/06513 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01079 , H01L2924/1305 , H01L2924/1306 , H01L2924/00 , H01L2224/80 , H01L2224/82
摘要： Two substrates are brought together and placed in a plating bath. In one embodiment, a conductive material is plated in microscopic cavities present at the interface between a first metal pad and a second metal pad to form at least one interfacial plated metal liner portion that adheres to a surface of the first metal pad and a surface of the second metal pad. In another embodiment, at least one metal pad is recessed relative to a dielectric surface before being brought together. The two substrates are placed in a plating bath and a conductive material is plated in the cavity between the first metal pad and the second metal pad to form a contiguous plated metal liner layer that adheres to a surface of the first metal pad and a surface of the second metal pad.

23. 发明申请

US20130026635A1 Hybrid Copper Interconnect Structure and Method of Fabricating Same 有权
标题翻译：混合铜互连结构及其制造方法
公开(公告)号：US20130026635A1
公开(公告)日：2013-01-31
申请号：US13191999
申请日：2011-07-27
申请人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76841 , H01L21/76843 , H01L21/76847 , H01L21/76877 , H01L21/76882 , H01L2924/0002 , H01L2924/00
摘要： A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region. The copper regions containing the different impurities levels can be achieved utilizing a combination of physical vapor deposition of a copper region having a low impurity level (i.e., less than 20 ppm) and copper reflow, with electroplating another copper region having a high impurity level (i.e., 100 ppm or greater).
摘要翻译：提供了包含在相同开口内具有不同杂质水平的铜区域的混合互连结构。在一个实施例中，互连结构包括具有位于其中的至少一个开口的图案化电介质材料。双材料衬垫至少位于所述至少一个开口内的图案化电介质材料的侧壁上。所述结构还包括具有位于所述至少一个开口的底部区域内的第一杂质水平的第一铜区域和具有位于所述至少一个开口的顶部区域内的第二杂质水平的第二铜区域和位于所述第一铜地区。根据本公开，第一铜区域的第一杂质水平不同于第二铜区域的第二杂质水平。可以利用具有低杂质水平（即小于20ppm）的铜区域和铜回流的物理气相沉积与电镀另一个具有高杂质水平的铜区域的组合来实现含有不同杂质水平的铜区域即100ppm以上）。

24. 发明授权

US08299625B2 Borderless interconnect line structure self-aligned to upper and lower level contact vias 有权
标题翻译：无边界互连线结构自对准到上层和下层接触孔
公开(公告)号：US08299625B2
公开(公告)日：2012-10-30
申请号：US12899911
申请日：2010-10-07
申请人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L23/48
CPC分类号： H01L23/528 , H01L21/76885 , H01L21/76897 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.
摘要翻译：金属层沉积在其上暴露下面的金属通孔的顶表面的平坦表面上。图案化金属层以形成至少一个金属块，其具有要形成的金属线的水平横截面积和要形成的至少一个上覆的金属通孔。下面的金属通孔的每个上部凹陷在位于正上方的金属块的区域的外部。至少一个金属块的上部被光刻地图案化以形成集成线和通孔结构，其包括具有基本上恒定的宽度的金属线和至少一个覆盖的金属通孔，其具有相同的基本上恒定的宽度并且与金属线无边界地对准。沉积和平坦化上层电介质材料层，使得至少一个上覆金属通孔的顶表面被暴露。

25. 发明申请

US20120175775A1 INTEGRATED CIRCUIT LINE WITH ELECTROMIGRATION BARRIERS 失效
标题翻译：集成电路与电气障碍
公开(公告)号：US20120175775A1
公开(公告)日：2012-07-12
申请号：US13424651
申请日：2012-03-20
申请人： David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
发明人： David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/532
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76847 , H01L21/76852 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.
摘要翻译：包括电迁移屏障的集成电路包括线，该线包括第一导电材料，该线还包括由一个或多个电迁移屏障隔开的多个线段，其中所述一个或多个电迁移屏障包括隔离的第二导电材料线路各部分的电迁移效应。

26. 发明申请

US20120068346A1 STRUCTURE FOR NANO-SCALE METALLIZATION AND METHOD FOR FABRICATING SAME 有权
标题翻译：用于纳米尺度金属化的结构及其制造方法
公开(公告)号：US20120068346A1
公开(公告)日：2012-03-22
申请号：US12885665
申请日：2010-09-20
申请人： SHOM PONOTH , David V. Horak , Elbert E. Huang , Sivananda K. Kanakasabapathy , Charles W. Koburger, III , Chih-Chao Yang
发明人： SHOM PONOTH , David V. Horak , Elbert E. Huang , Sivananda K. Kanakasabapathy , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L23/53266 , H01L21/32139 , H01L21/76885 , H01L21/76897 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography.
摘要翻译：为诸如集成电路的互连结构提供了用于形成与不透明层下面的特征对准的结构的方法。在一个实施例中，该方法包括在第一层上形成不透明层，第一层具有映射到其中的至少一个特征的表面形貌，其中不透明层被形成为使得表面形貌在不透明层上可见。通过参考这种表面形貌，第二特征被定位并形成在不透明层中。

27. 发明申请

US20110193230A1 FORMATION OF AIR GAP WITH PROTECTION OF METAL LINES 失效
标题翻译：形成有保护金属线的空气隙
公开(公告)号：US20110193230A1
公开(公告)日：2011-08-11
申请号：US12700792
申请日：2010-02-05
申请人： Takeshi Nogami , Shyng-Tsong Chen , David V. Horak , Son V. Nguyen , Shom Ponoth , Chih-Chao Yang
发明人： Takeshi Nogami , Shyng-Tsong Chen , David V. Horak , Son V. Nguyen , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L24/80 , H01L21/0337 , H01L21/31144 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L23/53295
摘要： A method is provided for fabricating a microelectronic element having an air gap in a dielectric layer thereof. A dielectric cap layer can be formed which has a first portion overlying surfaces of metal lines, the first portion extending a first height above a height of a surface of the dielectric layer and a second portion overlying the dielectric layer surface and extending a second height above the height of the surface of the dielectric layer, the second height being greater than the first height. After forming the cap layer, a mask can be formed over the cap layer. The mask can have a multiplicity of randomly disposed holes. Each hole may expose a surface of only the second portion of the cap layer which has the greater height. The mask may fully cover a surface of the first portion of the cap layer having the lower height. Subsequently, an etchant can be directed towards the first and second portions of the cap layer to form holes in the cap layer aligned with the holes in the mask. Material can be removed from the dielectric layer where exposed to the etchant by the holes in the cap layer. At such time, the mask can protect the first portion of the cap layer and the metal lines from being attacked by the etchant.
摘要翻译：提供了一种用于制造其电介质层中具有气隙的微电子元件的方法。可以形成介电盖层，其具有覆盖金属线表面的第一部分，第一部分在电介质层的表面的高度之上延伸第一高度，以及覆盖介电层表面的第二部分，并且延伸第二高度电介质层的表面的高度，第二高度大于第一高度。在形成盖层之后，可以在盖层之上形成掩模。掩模可以具有多个随机布置的孔。每个孔可以暴露仅具有较大高度的盖层的第二部分的表面。掩模可以完全覆盖具有较低高度的盖层的第一部分的表面。随后，可以将蚀刻剂引导到盖层的第一和第二部分，以在盖层中形成与掩模中的孔对准的孔。可以通过盖层中的孔从暴露于蚀刻剂的介电层去除材料。此时，掩模可以保护盖层的第一部分和金属线不被蚀刻剂侵蚀。

28. 发明授权

US07687877B2 Interconnect structure with a mushroom-shaped oxide capping layer and method for fabricating same 有权
标题翻译：具有蘑菇状氧化物覆盖层的互连结构及其制造方法
公开(公告)号：US07687877B2
公开(公告)日：2010-03-30
申请号：US12115944
申请日：2008-05-06
申请人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
IPC分类号： H01L23/485 , H01L21/768
CPC分类号： H01L23/53295 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L21/76885 , H01L23/53223 , H01L23/53238 , H01L23/53271 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure is provided that includes a dielectric material 52′ having a dielectric constant of 4.0 or less and including a plurality of conductive features 56 embedded therein. The dielectric material 52′ has an upper surface 52r that is located beneath an upper surface of each of the plurality of conductive features 56. A first dielectric cap 58 is located on the upper surface of the dielectric material 52′ and extends onto at least a portion of the upper surface of each of the plurality of conductive features 56. As shown, the first dielectric cap 58 forms an interface 59 with each of the plurality of conductive features 56 that is opposite to an electrical field that is generated by neighboring conductive features. The inventive structure also includes a second dielectric cap 60 located on an exposed portion of the upper surface of each of the plurality of conductive features 56 not covered with the first dielectric cap 58. The second dielectric cap 60 further covers on an exposed surface of the first dielectric cap 58.
摘要翻译：提供一种互连结构，其包括介电常数为4.0或更小的介电材料52'，并且包括嵌入其中的多个导电特征56。电介质材料52'具有位于多个导电特征56中的每一个的上表面下方的上表面52r。第一电介质盖58位于电介质材料52'的上表面上并延伸至至少一个多个导电特征56中的每一个的上表面的一部分。如图所示，第一电介质盖58形成接口59，多个导电特征56中的每一个与由相邻导电特征。本发明的结构还包括位于多个导电特征56的每一个的上表面的未被第一电介质盖58覆盖的暴露部分上的第二电介质帽60.第二电介质帽60还覆盖在第一电介质盖58。

29. 发明申请

US20090184400A1 VIA GOUGING METHODS AND RELATED SEMICONDUCTOR STRUCTURE 有权
标题翻译：通过采用方法和相关半导体结构
公开(公告)号：US20090184400A1
公开(公告)日：2009-07-23
申请号：US12017141
申请日：2008-01-21
申请人： Shyng-Tsong Chen , Steven J. Holmes , David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
发明人： Shyng-Tsong Chen , Steven J. Holmes , David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/311 , H01L23/538
CPC分类号： H01L21/32139 , H01L21/31144 , H01L21/76805 , H01L21/76814 , H01L21/76831 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Methods for via gouging and a related semiconductor structure are disclosed. In one embodiment, the method includes forming a via opening in a dielectric material, the via opening aligned with a conductor; forming a protective coating over the dielectric material and in the via opening; performing via gouging; and removing the protective coating over horizontal surfaces of the dielectric material. A semiconductor structure may include a via having an interface with a conductor, the interface including a three-dimensionally shaped region extending into and past a surface of the conductor, wherein an outer edge of the three-dimensionally shaped region is distanced from an outermost surface of the via.
摘要翻译：公开了通孔沟槽的方法和相关的半导体结构。在一个实施例中，该方法包括在电介质材料中形成通孔，通孔与导体对准; 在介电材料和通孔开口上形成保护涂层; 通过刨花进行; 并且在电介质材料的水平表面上去除保护涂层。半导体结构可以包括与导体具有界面的通孔，所述界面包括延伸到导体表面中并经过导体表面的三维成形区域，其中三维成形区域的外边缘与最外表面的通道。

30. 发明申请

US20140070282A1 SELF-ALIGNED CONTACTS 有权
标题翻译：自对准联系人
公开(公告)号：US20140070282A1
公开(公告)日：2014-03-13
申请号：US13607856
申请日：2012-09-10
申请人： Su Chen Fan , David V. Horak , Shom Ponoth , David L. Rath , Muthumanickam Sankarapandian
发明人： Su Chen Fan , David V. Horak , Shom Ponoth , David L. Rath , Muthumanickam Sankarapandian
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L21/28088 , H01L21/76897 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： Self-aligned contacts in a metal gate structure and methods of manufacture are disclosed herein. The method includes forming a metal gate structure having a sidewall structure. The method further includes recessing the metal gate structure and forming a masking material within the recess. The method further includes forming a borderless contact adjacent to the metal gate structure, overlapping the masking material and the sidewall structure.
摘要翻译：本文公开了金属栅极结构中的自对准触点和制造方法。该方法包括形成具有侧壁结构的金属栅极结构。该方法还包括使金属栅极结构凹陷并在凹槽内形成掩模材料。该方法还包括在金属栅极结构附近形成无边界接触，与掩模材料和侧壁结构重叠。

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