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21. 发明授权

US08868477B2 Multi-compartment neurons with neural cores 有权
标题翻译：具有神经核的多室神经元
公开(公告)号：US08868477B2
公开(公告)日：2014-10-21
申请号：US13434733
申请日：2012-03-29
申请人： Steven K. Esser , Dharmendra S. Modha
发明人： Steven K. Esser , Dharmendra S. Modha
IPC分类号： G06E1/00 , G06N3/04 , G06N3/063
CPC分类号： G06N3/04 , G06F9/44505 , G06N3/049 , G06N3/063 , G06N3/088
摘要： Embodiments of the invention provide a neural core circuit comprising a synaptic interconnect network including plural electronic synapses for interconnecting one or more source electronic neurons with one or more target electronic neurons. The interconnect network further includes multiple axon paths and multiple dendrite paths. Each synapse is at a cross-point junction of the interconnect network between a dendrite path and an axon path. The core circuit further comprises a routing module maintaining routing information. The routing module routes output from a source electronic neuron to one or more selected axon paths. Each synapse provides a configurable level of signal conduction from an axon path of a source electronic neuron to a dendrite path of a target electronic neuron.
摘要翻译：本发明的实施例提供了一种包括突触互连网络的神经核心电路，其包括用于将一个或多个源电子神经元与一个或多个目标电子神经元相互连接的多个电子突触。互连网络还包括多个轴突路径和多个树枝状路径。每个突触处于互连网络在树枝状路径和轴突路径之间的交叉点处。核心电路还包括维护路由信息的路由模块。路由模块将源电子神经元的输出路由到一个或多个选择的轴突路径。每个突触提供从源电子神经元的轴突路径到目标电子神经元的枝晶路径的可配置水平的信号传导。

22. 发明申请

US20130339281A1 MULTI-PROCESSOR CORTICAL SIMULATIONS WITH RECIPROCAL CONNECTIONS WITH SHARED WEIGHTS 有权
标题翻译：具有共享重量的双向连接的多处理器反射模拟
公开(公告)号：US20130339281A1
公开(公告)日：2013-12-19
申请号：US13524798
申请日：2012-06-15
申请人： Pallab Datta , Steven K. Esser , Dharmendra S. Modha
发明人： Pallab Datta , Steven K. Esser , Dharmendra S. Modha
IPC分类号： G06N3/04
CPC分类号： G06N3/02 , G06N3/049 , G06N3/06 , G06N3/10
摘要： Embodiments of the invention relate to distributed simulation frameworks that provide reciprocal communication. One embodiment comprises interconnecting neuron groups on different processors via a plurality of reciprocal communication pathways, and facilitating the exchange of reciprocal spiking communication between two different processors using at least one Ineuron module. Each processor includes at least one neuron group. Each neuron group includes at least one electronic neuron.
摘要翻译：本发明的实施例涉及提供相互通信的分布式仿真框架。一个实施例包括经由多个相互通信路径在不同处理器上互连神经元组，并且促进使用至少一个Ineuron模块交换两个不同处理器之间的相互加速通信。每个处理器包括至少一个神经元组。每个神经元组包括至少一个电子神经元。

23. 发明授权

US08655813B2 Synaptic weight normalized spiking neuronal networks 有权
标题翻译：突触体重标准化的神经元网络
公开(公告)号：US08655813B2
公开(公告)日：2014-02-18
申请号：US12982546
申请日：2010-12-30
申请人： Rajagopal Ananthanarayanan , Steven K. Esser , Dharmendra S. Modha
发明人： Rajagopal Ananthanarayanan , Steven K. Esser , Dharmendra S. Modha
IPC分类号： G06F15/18 , G06N3/08
CPC分类号： G06N3/049
摘要： Neuronal networks of electronic neurons interconnected via electronic synapses with synaptic weight normalization. The synaptic weights are based on learning rules for the neuronal network, such that a synaptic weight for a synapse determines the effect of a spiking source neuron on a target neuron connected via the synapse. Each synaptic weight is maintained within a predetermined range by performing synaptic weight normalization for neural network stability.
摘要翻译：通过电子突触与突触体重标准化相互联系的神经元网络。突触权重基于神经元网络的学习规则，使得突触的突触权重决定了刺激源神经元对通过突触连接的目标神经元的影响。通过对神经网络稳定性执行突触权重归一化，将每个突触重量保持在预定范围内。

24. 发明申请

US20120173471A1 SYNAPTIC WEIGHT NORMALIZED SPIKING NEURONAL NETWORKS 有权
标题翻译： SYNAPTIC WEIGHT正规化SPIKING神经网络
公开(公告)号：US20120173471A1
公开(公告)日：2012-07-05
申请号：US12982546
申请日：2010-12-30
申请人： Rajagopal Ananthanarayanan , Steven K. Esser , Dharmendra S. Modha
发明人： Rajagopal Ananthanarayanan , Steven K. Esser , Dharmendra S. Modha
IPC分类号： G06N3/063 , G06N3/08
CPC分类号： G06N3/049
摘要： Neuronal networks of electronic neurons interconnected via electronic synapses with synaptic weight normalization. The synaptic weights are based on learning rules for the neuronal network, such that a synaptic weight for a synapse determines the effect of a spiking source neuron on a target neuron connected via the synapse. Each synaptic weight is maintained within a predetermined range by performing synaptic weight normalization for neural network stability.
摘要翻译：通过电子突触与突触体重标准化相互联系的神经元网络。突触权重基于神经元网络的学习规则，使得突触的突触权重决定了刺激源神经元对通过突触连接的目标神经元的影响。通过对神经网络稳定性执行突触权重归一化，将每个突触重量保持在预定范围内。

25. 发明申请

US20120150781A1 INTEGRATE AND FIRE ELECTRONIC NEURONS 有权
标题翻译：一体化和消防电子神经元
公开(公告)号：US20120150781A1
公开(公告)日：2012-06-14
申请号：US12963558
申请日：2010-12-08
申请人： John V. Arthur , Gregory S. Corrado , Steven K. Esser , Paul A. Merolla , Dharmendra S. Modha
发明人： John V. Arthur , Gregory S. Corrado , Steven K. Esser , Paul A. Merolla , Dharmendra S. Modha
IPC分类号： G06N3/02 , G06N3/00
CPC分类号： G06N3/049
摘要： An integrate and fire electronic neuron is disclosed. Upon receiving an external spike signal, a digital membrane potential of the electronic neuron is updated based on the external spike signal. The electric potential of the membrane is decayed based on a leak rate. Upon the electric potential of the membrane exceeding a threshold, a spike signal is generated.
摘要翻译：公开了一种整合和消防电子神经元。在接收到外部尖峰信号时，基于外部尖峰信号更新电子神经元的数字膜电位。膜的电位根据泄漏率衰减。当膜的电位超过阈值时，产生尖峰信号。

26. 发明授权

US08914315B2 Multi-compartment neuron suitable for implementation in a distributed hardware model by reducing communication bandwidth 有权
标题翻译：多分段神经元适用于通过降低通信带宽在分布式硬件模型中实现
公开(公告)号：US08914315B2
公开(公告)日：2014-12-16
申请号：US13360622
申请日：2012-01-27
申请人： Dharmendra S. Modha , Steven K. Esser
发明人： Dharmendra S. Modha , Steven K. Esser
IPC分类号： G06N3/04
CPC分类号： G06N3/063 , G06N3/049
摘要： Embodiments of the present invention provide a neural module comprising a multilevel hierarchical structure of neural compartments. Each neural compartment is interconnected to one or more neural compartments of a previous level and a next hierarchical level in the hierarchical structure. Each neural compartment integrates spike signals from interconnected neural compartments of a previous hierarchical level, generates a spike signal in response to the integrated spike signals reaching a threshold of said neural compartment, and delivers a generated spike signal to interconnected neural compartments of a next hierarchical level. Each neural compartment is further interconnected to one or more external spiking systems, such that said neural compartment integrates spike signals from interconnected external spiking systems, and delivers a generated spike signal to interconnected external spiking systems. The neural compartments of a neural module include one soma compartment and a plurality of dendrite compartments. Each neural compartment is excitatory or inhibitory.
摘要翻译：本发明的实施例提供一种神经模块，其包括神经腔室的多级分级结构。每个神经隔室与分层结构中的先前水平和下一层次级别的一个或多个神经隔室相互连接。每个神经隔室整合来自先前分层级别的互连神经腔室的尖峰信号，响应于达到所述神经腔室的阈值的积分尖峰信号产生尖峰信号，并将产生的尖峰信号传递到下一层级的互连神经腔室。每个神经隔室进一步互连到一个或多个外部加标系统，使得所述神经腔室集成来自互连的外部加标系统的尖峰信号，并将产生的尖峰信号传送到互连的外部加标系统。神经模块的神经腔室包括一个血管隔室和多个枝晶隔室。每个神经室是兴奋性或抑制性的。

27. 发明授权

US08473439B2 Integrate and fire electronic neurons 有权
标题翻译：整合和消防电子神经元
公开(公告)号：US08473439B2
公开(公告)日：2013-06-25
申请号：US12963558
申请日：2010-12-08
申请人： John V. Arthur , Gregory S. Corrado , Steven K. Esser , Paul A. Merolla , Dharmendra S. Modha
发明人： John V. Arthur , Gregory S. Corrado , Steven K. Esser , Paul A. Merolla , Dharmendra S. Modha
IPC分类号： G06N5/00
CPC分类号： G06N3/049
摘要： An integrate and fire electronic neuron is disclosed. Upon receiving an external spike signal, a digital membrane potential of the electronic neuron is updated based on the external spike signal. The electric potential of the membrane is decayed based on a leak rate. Upon the electric potential of the membrane exceeding a threshold, a spike signal is generated.
摘要翻译：公开了一种整合和消防电子神经元。在接收到外部尖峰信号时，基于外部尖峰信号更新电子神经元的数字膜电位。膜的电位根据泄漏率衰减。当膜的电位超过阈值时，产生尖峰信号。

28. 发明申请

US20140032464A1 MULTI-COMPARTMENT NEURONS WITH NEURAL CORES 有权
标题翻译：多层神经元神经元
公开(公告)号：US20140032464A1
公开(公告)日：2014-01-30
申请号：US13434733
申请日：2012-03-29
申请人： Steven K. Esser , Dharmendra S. Modha
发明人： Steven K. Esser , Dharmendra S. Modha
IPC分类号： G06N3/063
CPC分类号： G06N3/04 , G06F9/44505 , G06N3/049 , G06N3/063 , G06N3/088
摘要： Embodiments of the invention provide a neural core circuit comprising a synaptic interconnect network including plural electronic synapses for interconnecting one or more source electronic neurons with one or more target electronic neurons. The interconnect network further includes multiple axon paths and multiple dendrite paths. Each synapse is at a cross-point junction of the interconnect network between a dendrite path and an axon path. The core circuit further comprises a routing module maintaining routing information. The routing module routes output from a source electronic neuron to one or more selected axon paths. Each synapse provides a configurable level of signal conduction from an axon path of a source electronic neuron to a dendrite path of a target electronic neuron.
摘要翻译：本发明的实施例提供了一种包括突触互连网络的神经核心电路，其包括用于将一个或多个源电子神经元与一个或多个目标电子神经元相互连接的多个电子突触。互连网络还包括多个轴突路径和多个树枝状路径。每个突触处于互连网络在树枝状路径和轴突路径之间的交叉点处。核心电路还包括维护路由信息的路由模块。路由模块将源电子神经元的输出路由到一个或多个选择的轴突路径。每个突触提供从源电子神经元的轴突路径到目标电子神经元的枝晶路径的可配置水平的信号传导。

29. 发明申请

US20130198121A1 MULTI-COMPARTMENT NEURON SUITABLE FOR IMPLEMENTATION IN A DISTRIBUTED HARDWARE MODEL BY REDUCING COMMUNICATION BANDWIDTH 有权
标题翻译：用于通过减少通信带宽实现分布式硬件模型的多层天线
公开(公告)号：US20130198121A1
公开(公告)日：2013-08-01
申请号：US13360622
申请日：2012-01-27
申请人： Dharmendra S. Modha , Steven K. Esser
发明人： Dharmendra S. Modha , Steven K. Esser
IPC分类号： G06N3/04
CPC分类号： G06N3/063 , G06N3/049
摘要： Embodiments of the present invention provide a neural module comprising a multilevel hierarchical structure of neural compartments. Each neural compartment is interconnected to one or more neural compartments of a previous level and a next hierarchical level in the hierarchical structure. Each neural compartment integrates spike signals from interconnected neural compartments of a previous hierarchical level, generates a spike signal in response to the integrated spike signals reaching a threshold of said neural compartment, and delivers a generated spike signal to interconnected neural compartments of a next hierarchical level. Each neural compartment is further interconnected to one or more external spiking systems, such that said neural compartment integrates spike signals from interconnected external spiking systems, and delivers a generated spike signal to interconnected external spiking systems. The neural compartments of a neural module include one soma compartment and a plurality of dendrite compartments. Each neural compartment is excitatory or inhibitory.
摘要翻译：本发明的实施例提供一种神经模块，其包括神经腔室的多级分级结构。每个神经隔室与分层结构中的先前水平和下一层次级别的一个或多个神经隔室相互连接。每个神经隔室整合来自先前分层级别的互连神经腔室的尖峰信号，响应于达到所述神经腔室的阈值的积分尖峰信号产生尖峰信号，并将产生的尖峰信号传递到下一层级的互连神经腔室。每个神经隔室进一步互连到一个或多个外部加标系统，使得所述神经腔室集成来自互连的外部加标系统的尖峰信号，并将产生的尖峰信号传送到互连的外部加标系统。神经模块的神经腔室包括一个血管隔室和多个枝晶隔室。每个神经室是兴奋性或抑制性的。

30. 发明授权

US09269044B2 Neuromorphic event-driven neural computing architecture in a scalable neural network 有权
标题翻译：神经元事件驱动的神经计算架构在可扩展的神经网络中
公开(公告)号：US09269044B2
公开(公告)日：2016-02-23
申请号：US13585010
申请日：2012-08-14
申请人： Filipp Akopyan , John V. Arthur , Rajit Manohar , Paul A. Merolla , Dharmendra S. Modha , Alyosha Molnar , William P. Risk, III
发明人： Filipp Akopyan , John V. Arthur , Rajit Manohar , Paul A. Merolla , Dharmendra S. Modha , Alyosha Molnar , William P. Risk, III
IPC分类号： G06N3/04 , G06N3/063
CPC分类号： G06N3/06 , G06N3/04 , G06N3/049 , G06N3/063
摘要： An event-driven neural network includes a plurality of interconnected core circuits is provided. Each core circuit includes an electronic synapse array has multiple digital synapses interconnecting a plurality of digital electronic neurons. A synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. A neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. Each core circuit also has a scheduler that receives a spike event and delivers the spike event to a selected axon in the synapse array based on a schedule for deterministic event delivery.
摘要翻译：事件驱动神经网络包括多个互连的核心电路。每个核心电路包括具有互连多个数字电子神经元的多个数字突触的电子突触阵列。突触将突触前神经元的轴突与突触后神经元的枝晶相互连接。神经元集成输入尖峰，并响应于超过阈值的积分输入尖峰而产生尖峰事件。每个核心电路还具有接收尖峰事件的调度器，并且基于用于确定性事件递送的调度将突发事件传递到突触阵列中的选定轴突。

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