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    • 22. 发明申请
    • Updating elements in a data storage facility using a predefined state machine, with parallel activation
    • 使用预定义的状态机更新数据存储设备中的元素,并行激活
    • US20060112387A1
    • 2006-05-25
    • US10992176
    • 2004-11-18
    • Edward ButtFranck ExcoffierSteven Johnson
    • Edward ButtFranck ExcoffierSteven Johnson
    • G06F9/445
    • G06F8/65
    • A technique for updating elements in a data storage facility, including a single server or a multi-server system, such as by providing updated internal code packages to the elements. The update is performed using a fixed state machine, where the elements are updated in a coordinated manner within the constraints of the state machine. In a multi-server device, the code packages are distributed to elements associated with the different servers in one traversal of the state machine, during distribute states of the state machine. The distributed code packages are activated in activate states of the state machine in one traversal of the state machine, so there is parallel activation. The code packages can be grouped in a flexible way by configuring an external update bundle used by the state machine. The distributing of the code is based on the grouping.
    • 一种用于更新数据存储设施中的元素的技术,包括单个服务器或多服务器系统,例如通过向元素提供更新的内部代码包。 使用固定状态机执行更新,其中在状态机的约束内以协调的方式更新元素。 在多服务器设备中,在状态机的分布状态期间,代码包被分发到与状态机的一次遍历中的与不同服务器相关联的元件。 在状态机的一次遍历中,分布式代码包在状态机的激活状态下被激活,因此存在并行激活。 通过配置状态机使用的外部更新包,可以灵活地对代码包进行分组。 代码的分发是基于分组的。
    • 24. 发明申请
    • Method of awarding prizes for jackpot and gaming machines based on amount wagered during a time period
    • 根据一段时间内下注的数额奖励大奖和游戏机奖品的方法
    • US20060025210A1
    • 2006-02-02
    • US11236180
    • 2005-09-26
    • Steven Johnson
    • Steven Johnson
    • A63F9/24
    • G07F17/3267G07F17/32G07F17/3258
    • Periodic prize draws are conducted by a jackpot controller (13) in a gaming system having one or more electronic gaming devices (10). The probability of each electronic gaming device winning a particular prize draw is dependent upon the amount wagered on that gaming machine during a period preceding that prize draw. The prize may be a progressive jackpot which comprises an initial starting value and a contribution from the amounts wagered on the electronic gaming devices. If an electronic gaming device wins a prize draw, its player may be granted a feature game to determine the actual prize. Jackpots are suspended pending the completion of the feature game. The probability that a gaming device will win the prize draw, or the relative win probabilities of the gaming devices, may be displayed graphically.
    • 在具有一个或多个电子游戏装置(10)的游戏系统中,累积奖池控制器(13)进行定期抽奖。 每个电子游戏设备赢得特定抽奖的概率取决于在该抽奖之前的一段时间内在该游戏机上下注的金额。 奖品可以是累进奖金,其包括初始起始价值和从电子游戏设备上下注的金额的贡献。 如果电子游戏设备赢得抽奖,则可以向其玩家授予特色游戏以确定实际奖品。 在功能游戏完成之前,积木被暂停。 可以图形地显示游戏设备获得奖品的可能性,或游戏设备的相对胜率概率。
    • 28. 发明授权
    • Timing generator
    • 定时发生器
    • US4933955A
    • 1990-06-12
    • US161019
    • 1988-02-26
    • Toney WarrenSteven Johnson
    • Toney WarrenSteven Johnson
    • H03K5/00H04J3/06H04L7/04
    • H04J3/0688H04L7/0037
    • The circuitry of the present invention taps a DS0 data stream and outputs a timing signal to drive terminal multiplexers. Even if the data bit stream is lost, the present invention continues to provide proper clocking signals. A composite clock (bit and byte clock) is provided by the present invention with the bit clock at 64 KHz and the byte clock at 8 KHz in the preferred embodiment. To avoid the problem of phase shift over long distances (limiting cable length) the present invention phase adjusts the digital bit stream clocking signal with a 360 degree delay, giving the appearance of advancing the signal in phase. An additional delay of one frame width is applied to the signal. A negative phase delay equivalent to cable runs from 0-1500 feet in 500 foot increments is also applied. In the preferred embodiment, a shift register is tapped in reverse order to accomplish this phase delay.
    • 本发明的电路分接DS0数据流并将定时信号输出到驱动终端多路复用器。 即使数据比特流丢失,本发明继续提供适当的时钟信号。 在优选实施例中,本发明提供复合时钟(位和字节时钟),位时钟为64KHz,字节时钟为8KHz。 为了避免长距离相移的问题(限制电缆长度),本发明相位调整了360度延迟的数字比特流计时信号,从而使信号同步进行。 一个帧宽的附加延迟被施加到该信号。 相当于电缆的负相位延迟从0-1500英尺增加到500英尺。 在优选实施例中,以相反的顺序抽头移位寄存器来实现该相位延迟。
    • 29. 发明授权
    • Clock holdover circuit
    • 时钟保持电路
    • US4849993A
    • 1989-07-18
    • US131141
    • 1987-12-10
    • Steven JohnsonToney Warren
    • Steven JohnsonToney Warren
    • H03L7/14H04L7/00H04L7/033
    • H03L7/143H04L7/0083H03L7/145
    • The present invention provides a clock holdover circuit which will provide a replacement clock signal within predetermined parameters independently of time and temperature variations. The circuit of the present invention has only a single component which is time and temperature dependent. By selecting the components parameters to be within the desired tolerances, the accuracy of the circuit is maintained. In the present invention, digital circuitry is combined with an accurate local crystal frequency source to provide a replacement clock signal. The present invention allows phase consistency upon loss of a reference clock signal as well as on return of the reference clock signal. A reference clock signal is phase locked to a VCO to produce a desired output. The frequency of the output is compared to a local frequency standard to generate an offset frequency used to control a frequency synthesizer. The offset frequency is digitally stored. Upon loss of the reference clock signal, the stored offset frequency is used to drive the frequency synthesizer along with the local frequency standard so as to provide an acceptable replacement clock signal. The frequency comparator, storage, and synthesizer are all digital so as to be time and temperature independent. The local frequency standard is crystal based having known time and temperature tolerances. By choosing a local frequency standard having tolerances within a predetermined range, an acceptable clock holdover signal may be provided indefinitely. The replacement clock signal is phase compared to the reference clock signal so that no loss of phase occurs upon reference loss.
    • 本发明提供了一种时钟保持电路,其将在独立于时间和温度变化的情况下提供在预定参数内的替换时钟信号。 本发明的电路仅具有时间和温度依赖性的单一部件。 通过选择组件参数在所需的公差范围内,可以保持电路的精度。 在本发明中,数字电路与准确的本地晶体频率源组合以提供替换时钟信号。 本发明允许参考时钟信号丢失以及参考时钟信号返回时的相位一致性。 参考时钟信号被锁相到VCO以产生期望的输出。 将输出的频率与本地频率标准进行比较,以产生用于控制频率合成器的偏移频率。 偏移频率被数字存储。 在丢失参考时钟信号时,存储的偏移频率用于驱动频率合成器以及本地频率标准,以便提供可接受的替换时钟信号。 频率比较器,存储器和合成器都是数字的,以便与时间和温度无关。 本地频率标准是基于晶体的,具有已知的时间和温度公差。 通过选择具有在预定范围内的公差的本地频率标准,可以无限期地提供可接受的时钟保持信号。 替换时钟信号与参考时钟信号进行相位比较,从而在参考损耗时不发生相位损失。