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21. 发明授权

US07187597B1 Integrated circuit with circuitry for overriding a defective configuration memory cell 有权
标题翻译：具有用于覆盖缺陷配置存储单元的电路的集成电路
公开(公告)号：US07187597B1
公开(公告)日：2007-03-06
申请号：US11218415
申请日：2005-09-01
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C8/10 , G11C5/063 , G11C29/24 , G11C29/816 , G11C29/846
摘要： An integrated circuit and a method for configuring programmable logic thereof are described. A data register and an address register are coupled to an array of memory cells of the integrated circuit. Address storage is configurable for storing an address associated configuration data targeted for being written to at least one defective memory cell of the array of memory cells. Data storage is configured to store the configuration data associated with the at least one defective memory cell. A controller is configured to cause the address to be loaded into the address register and the configuration data to be loaded into the data register. The controller is configured to maintain a write state for continually writing the configuration data to the array of memory cells responsive to the address during operation of the integrated circuit.
摘要翻译：描述了用于配置其可编程逻辑的集成电路和方法。数据寄存器和地址寄存器耦合到集成电路的存储单元阵列。地址存储器可配置为存储针对要写入到存储器单元阵列的至少一个有缺陷的存储器单元的地址相关联的配置数据。数据存储被配置为存储与至少一个有缺陷的存储器单元相关联的配置数据。控制器被配置为使得地址被加载到地址寄存器中，并且配置数据被加载到数据寄存器中。控制器被配置为保持写入状态，以响应于在集成电路的操作期间的地址，将配置数据连续地写入存储器单元阵列。

22. 发明授权

US07143295B1 Methods and circuits for dedicating a programmable logic device for use with specific designs 有权
标题翻译：专用可编程逻辑器件用于特定设计的方法和电路
公开(公告)号：US07143295B1
公开(公告)日：2006-11-28
申请号：US10199535
申请日：2002-07-18
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： G06F11/30 , G06F12/14 , H04L9/32
CPC分类号： H04L9/0637 , G01R31/318555 , G06F21/76 , H04L9/3247 , H04L2209/12 , H04L2209/38
摘要： Disclosed are methods and circuits that enable PLD vendors to dedicate PLDs for use with one or more specified designs. The PLD is programmed to store an indicator related to a specific design, for example, a hash function of the design, and to compare an indicator calculated within the PLD from an expression of the design (such as a bitstream) with the stored indicator. Only if the comparison matches is the PLD programmed to implement the design.
摘要翻译：公开了使PLD供应商能够将PLD用于一个或多个指定设计的方法和电路。 PLD被编程为存储与特定设计相关的指示符，例如设计的散列函数，并且将PLD中计算的指示符与设计（例如比特流）的表达式与存储的指示符进行比较。只有比较匹配是编程实现设计的PLD。

23. 发明授权

US07138827B1 Programmable logic device with time-multiplexed interconnect 有权
公开(公告)号：US07138827B1
公开(公告)日：2006-11-21
申请号：US10810034
申请日：2004-03-26
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： H03K19/177
CPC分类号： G06F17/5054
摘要： A PLD includes at least one portion of the programmable interconnect that can be time multiplexed. The time multiplexed interconnect allows signals to be routed on shared interconnect at different times to different destinations, thereby increasing the functionality of the PLD. Multiple sources can use the same interconnect at different times to send signals to their respective destinations. To ensure proper sharing of the interconnect, the sources can include selection devices (such as multiplexers), and the destinations can include capture devices (such as flip-flops), wherein the selection devices and the capture devices are controlled by the same time multiplexing signal. To optimize the time multiplexing interconnect, as much of the same interconnect is shared as possible.

24. 发明授权

US07103685B1 Bitstream compression with don't care values 有权
标题翻译：比特流压缩与不关心的价值
公开(公告)号：US07103685B1
公开(公告)日：2006-09-05
申请号：US10759755
申请日：2004-01-16
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： G06F13/00
CPC分类号： H03M7/3084 , G06F17/5054
摘要： A method and system for processing a plurality of multi-bit configuration words for configuring a programmable logic device. One or more of bits of the multi-bit configuration words are identified as “Don't Care” configuration bits that do not affect the functionality of the programmable logic device. These “Don't Care” configuration bits may or may not be related to the specific configuration of the programmable logic device. A lossy compression operation is performed on the multi-bit configuration words thereby creating a compressed data set. The identified “Don't Care” configuration bits are used during the compression operation. For example, the compression operation may include (1) maintaining a compression buffer of previously compressed configuration words, and (2) comparing configuration words to be compressed with the configuration words in the compression buffer, wherein the “Don't Care” configuration bits are deemed to result in matches during the comparison.
摘要翻译：一种用于处理用于配置可编程逻辑器件的多个多位配置字的方法和系统。多位配置字中的一个或多个位被标识为不影响可编程逻辑器件的功能的“不关心”配置位。这些“不关心”配置位可能或可能与可编程逻辑器件的具体配置无关。对多位配置字执行有损压缩操作，从而创建压缩数据集。在压缩操作期间使用标识的“不关心”配置位。例如，压缩操作可以包括（1）维持先前压缩的配置字的压缩缓冲器，以及（2）将要压缩的配置字与压缩缓冲器中的配置字进行比较，其中“不关心”配置位在比较期间被视为导致比赛。

25. 发明授权

US06996713B1 Method and apparatus for protecting proprietary decryption keys for programmable logic devices 有权
标题翻译：用于保护可编程逻辑器件的专用解密密钥的方法和装置
公开(公告)号：US06996713B1
公开(公告)日：2006-02-07
申请号：US10112838
申请日：2002-03-29
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： G06F1/26
CPC分类号： G06F21/76
摘要： Described are methods and circuits of programming a programmable logic device with encrypted configuration data using one or more secure decryption keys. Configurable resources within PLDS in accordance with one embodiment are divided into first and second collections of configurable interconnect resources separated by a collection of switches. One collection of resources has access to one or more decryption keys required to decrypt the encrypted configuration data. The switches protect the proprietary keys by providing a secure boundary around the portion granted key access during the decryption process. Closing the switches after configuration clears user memory to prevent users from accessing stored versions of the proprietary keys.
摘要翻译：描述了使用一个或多个安全解密密钥对具有加密配置数据的可编程逻辑设备进行编程的方法和电路。根据一个实施例的PLDS内的可配置资源被划分为由开关集合分隔开的可配置互连资源的第一和第二集合。一组资源可以访问解密加密的配置数据所需的一个或多个解密密钥。交换机通过在解密过程中为授予密钥访问的部分提供安全边界来保护专有密钥。配置后关闭交换机会清除用户内存，以防止用户访问专有密钥的存储版本。

26. 发明授权

US06980026B1 Structures and methods for reducing power consumption in programmable logic devices 有权
标题翻译：用于降低可编程逻辑器件功耗的结构和方法
公开(公告)号：US06980026B1
公开(公告)日：2005-12-27
申请号：US10737603
申请日：2003-12-16
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17728 , H03K19/17784
摘要： Structures and methods that can be used to reduce power consumption in programmable logic devices (PLDs). Varying delays on the input paths of a PLD lookup table (LUT) can cause the nodes within the LUT (including the LUT output signal) to change state several times each time the input signals change state. Therefore, a programmable logic block for a PLD is provided that registers the LUT input signals instead of, or in addition to, the LUT output signal. The delays on the input paths are equalized and “glitching” on the LUT nodes is greatly reduced or eliminated. Thus, power consumption is reduced. Methods are also provided of reducing power consumption in PLDs by replacing single-bit registers on LUT output signals with multi-bit registers on LUT input signals, or by including multi-bit input registers in addition to the single-bit output registers.
摘要翻译：可用于降低可编程逻辑器件（PLD）功耗的结构和方法。每当输入信号改变状态时，PLD查找表（LUT）的输入路径上的不同延迟可以使LUT内的节点（包括LUT输出信号）改变状态多次。因此，提供了用于PLD的可编程逻辑块，其注册LUT输入信号，而不是或输出到LUT输出信号。输入路径上的延迟均衡，LUT节点上的“毛刺”大大减少或消除。因此，功耗降低。还提供了通过用LUT输入信号上的多位寄存器替换LUT输出信号上的单位寄存器，或者除了单位输出寄存器之外还包括多位输入寄存器来减少PLD中的功耗的方法。

27. 发明授权

US06601227B1 Method for making large-scale ASIC using pre-engineered long distance routing structure 有权
标题翻译：使用预设长距离路由结构制作大规模ASIC的方法
公开(公告)号：US06601227B1
公开(公告)日：2003-07-29
申请号：US09894514
申请日：2001-06-27
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： Optimal routing line segments and associated buffers are pre-engineered for each family of ASIC chips by simulating wires segments of various lengths using distributed resistance and capacitance wire models, and by estimating crosstalk from neighboring line segments. During ASIC design, space is reserved on the ASIC substrate for fabricating the buffers, which are selectively connected by local metal and diffusion structures to form long distance interconnections. Signals are passed from an ASIC circuit structure to a selected long distance interconnection by connecting an output terminal of the ASIC structure either to the input terminal of a buffer located at one end of the interconnection, or by connecting the output terminal directed to a line segment of the interconnection.
摘要翻译：通过使用分布式电阻和电容线模型模拟各种长度的导线段，并通过估计来自相邻线段的串扰，为每个ASIC芯片系列预先设计了最佳路由线段和相关缓冲区。在ASIC设计期间，在ASIC衬底上保留用于制造缓冲器的空间，缓冲器通过局部金属和扩散结构选择性地连接以形成长距离互连。通过将ASIC结构的输出端子连接到位于互连的一端的缓冲器的输入端子，或者通过连接引导到线路段的输出端子，将信号从ASIC电路结构传递到所选择的长距离互连的互连。

28. 发明授权

US06480954B2 Method of time multiplexing a programmable logic device 有权
标题翻译：时间复用可编程逻辑器件的方法
公开(公告)号：US06480954B2
公开(公告)日：2002-11-12
申请号：US09876745
申请日：2001-06-06
申请人： Stephen M. Trimberger , Richard A. Carberry , Robert Anders Johnson , Jennifer Wong
发明人： Stephen M. Trimberger , Richard A. Carberry , Robert Anders Johnson , Jennifer Wong
IPC分类号： G06F900
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/17752 , H03K19/17756 , H03K19/1776
摘要： A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.
摘要翻译：可编程逻辑器件（PLD）包括至少一个可配置元件和用于配置可配置元件的多个可编程逻辑元件。或者，PLD包括用于配置互连结构的互连结构和多个可编程逻辑元件。在任一实施例中，至少一个可编程逻辑元件包括N个存储器单元。 N个存储器单元中的预定的一个形成存储器片的一部分，其中可编程逻辑器件的每个片的至少一部分被分配给配置数据或用户数据存储器。通常，一个存储器片提供可编程逻辑器件的一个配置。根据一个实施例，存储器访问端口耦合在N个存储器单元中的至少一个和任一个可配置元件或互连之间，从而有助于在一个配置期间将新的配置数据加载到其他存储器片段中。新的配置数据可以包括片外或片上数据。本发明通常将至少一个片分配给用户数据存储器，并且包括用于禁止对N个存储器单元中的至少一个的访问的装置。

29. 发明授权

US06460131B1 FPGA input output buffer with registered tristate enable 失效
标题翻译：具有注册三态使能的FPGA输入输出缓冲器
公开(公告)号：US06460131B1
公开(公告)日：2002-10-01
申请号：US09328166
申请日：1999-06-08
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： G06F1340
CPC分类号： H03K19/17744 , G06F15/7814 , G06F15/7867 , H03K19/1737
摘要： In accordance with the present invention, an FPGA input/output buffer including a tristate enable register is provided. A bus line provides the FPGA output through a tristate buffer to the pad or pin. A register controls the state of the tristate buffer. A register for providing an input signal from the pad or pin may also be provided. By placing an address on address lines controlling the register clocks, any selected one of the input/output buffers can be accessed. In one embodiment, separate addresses are provided for loading a tristate control value into the output control register and for loading data into the input register.
摘要翻译：根据本发明，提供了包括三态使能寄存器的FPGA输入/输出缓冲器。总线通过三态缓冲器向FPGA或引脚提供FPGA输出。寄存器控制三态缓冲器的状态。还可以提供用于从焊盘或引脚提供输入信号的寄存器。通过在控制寄存器时钟的地址线上放置地址，可以访问所选择的一个输入/输出缓冲器。在一个实施例中，提供单独的地址用于将三态控制值加载到输出控制寄存器中并将数据加载到输入寄存器中。

30. 发明授权

US06421817B1 System and method of computation in a programmable logic device using virtual instructions 有权
标题翻译：使用虚拟指令的可编程逻辑器件中的系统和计算方法
公开(公告)号：US06421817B1
公开(公告)日：2002-07-16
申请号：US09541530
申请日：2000-04-03
申请人： Sundararajarao Mohan , Stephen M. Trimberger
发明人： Sundararajarao Mohan , Stephen M. Trimberger
IPC分类号： G06F1750
CPC分类号： G06F15/7867
摘要： An FPGA configuration provides a virtual instruction. In a generic computation, the output pattern of a first instruction is compared to the input pattern of a second instruction. If the input and output patterns of the first and second instructions do not match, then a pattern manipulation instruction is inserted between the first and second instructions. At this point, the input and output patterns of the first and second instructions should match and the computation task can be completed. The method of providing virtual instructions is applicable to any FPGA. In a standard FPGA, the data stored in the storage elements of the FPGA, such as flip-flops, is retained for the next configuration of the FPGA. In this manner, successive configurations can communicate data using the patterns of the storage elements, thereby allowing standard FPGAs to implement virtual instructions. Alternatively, a standard FPGA could write out data to an external memory using a predetermined pattern of addresses. In a subsequent configuration of the FPGA, the device could read data back from this pattern of addresses in the external memory. This embodiment allows various patterns of addresses, corresponding to data, to be used in any appropriate subsequent configuration of the FPGA. In this manner, the plurality of memory planes, previously provided on the dynamically reconfigurable FPGA, can be implemented off-chip.
摘要翻译： FPGA配置提供虚拟指令。在通用计算中，将第一指令的输出模式与第二指令的输入模式进行比较。如果第一和第二指令的输入和输出模式不匹配，则在第一和第二指令之间插入模式操作指令。此时，第一和第二指令的输入和输出模式应该匹配，并且可以完成计算任务。提供虚拟指令的方法适用于任何FPGA。在标准FPGA中，存储在FPGA的存储元件（例如触发器）中的数据被保留用于FPGA的下一个配置。以这种方式，连续配置可以使用存储元件的模式来传送数据，从而允许标准FPGA实现虚拟指令。或者，标准FPGA可以使用预定的地址模式将数据写入外部存储器。在FPGA的后续配置中，器件可以从外部存储器中的这种地址模式读取数据。该实施例允许在FPGA的任何适当的后续配置中使用与数据相对应的各种地址模式。以这种方式，先前提供在动态可重构FPGA上的多个存储器平面可以在片外实现。

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