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21. 发明申请

US20050286287A1 Complementary nonvolatile memory device, methods of operating and manufacturing the same, logic device and semiconductor device including the same, and reading circuit for the same 有权
标题翻译：互补非易失性存储器件，其操作和制造方法，包括其的逻辑器件和半导体器件及其相同的读取电路
公开(公告)号：US20050286287A1
公开(公告)日：2005-12-29
申请号：US11154941
申请日：2005-06-17
申请人： Yoon-dong Park , Jo-won Lee , Chung-woo Kim , Eun-hong Lee , Sun-ae Seo , Woo-joo Kim , Hee-soon Chae , Soo-doo Chae , I-hun Song
发明人： Yoon-dong Park , Jo-won Lee , Chung-woo Kim , Eun-hong Lee , Sun-ae Seo , Woo-joo Kim , Hee-soon Chae , Soo-doo Chae , I-hun Song
IPC分类号： G11C11/56 , G11C16/04 , G11C16/28 , H01L21/8247 , H01L27/06 , H01L27/115 , G11C5/06
CPC分类号： G11C11/5621 , H01L27/0688 , H01L27/11521 , H01L27/11551
摘要： Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.
摘要翻译：提供了一种互补的非易失性存储器件，其操作和制造方法，逻辑器件和具有该非易失性存储器件的半导体器件及其读取电路。互补非易失性存储器件包括顺序堆叠并具有互补关系的第一非易失性存储器和第二非易失性存储器。第一和第二非易失性存储器被布置成使得其上表面相邻。

22. 发明申请

US20100296347A1 Method of erasing device including complementary nonvolatile memory devices 有权
标题翻译：擦除装置的方法包括互补的非易失性存储装置
公开(公告)号：US20100296347A1
公开(公告)日：2010-11-25
申请号：US12662989
申请日：2010-05-14
申请人： Yoon-dong Park , Jo-won Lee , Chung-woo Kim , Eun-hong Lee , Sun-ae Seo , Woo-joo Kim , Hee-soon Chae , Soo-doo Chae , I-hun Song
发明人： Yoon-dong Park , Jo-won Lee , Chung-woo Kim , Eun-hong Lee , Sun-ae Seo , Woo-joo Kim , Hee-soon Chae , Soo-doo Chae , I-hun Song
IPC分类号： G11C16/04
CPC分类号： G11C11/5621 , H01L27/0688 , H01L27/11521 , H01L27/11551
摘要： Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.
摘要翻译：提供了一种互补的非易失性存储器件，其操作和制造方法，逻辑器件和具有该非易失性存储器件的半导体器件及其读取电路。互补非易失性存储器件包括顺序堆叠并具有互补关系的第一非易失性存储器和第二非易失性存储器。第一和第二非易失性存储器被布置成使得其上表面相邻。

23. 发明申请

US20090010058A1 MULTI-BIT NON-VOLATILE MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND METHOD OF FABRICATING THE SAME 失效
标题翻译：多位非易失性存储器件，其操作方法及其制造方法
公开(公告)号：US20090010058A1
公开(公告)日：2009-01-08
申请号：US12209735
申请日：2008-09-12
申请人： Soo-doo CHAE , Moon-kyung Kim , Jo-won Lee , Chung-woo Kim
发明人： Soo-doo CHAE , Moon-kyung Kim , Jo-won Lee , Chung-woo Kim
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0475 , H01L21/28282 , H01L29/66833 , H01L29/7923
摘要： A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.
摘要翻译：可以提供多位非易失性存储器件及其操作和制造方法。存储器件可以包括形成在半导体衬底中的沟道区，以及与沟道区形成肖特基接触的源极和漏极。此外，中心栅电极可以位于沟道区的一部分上，并且第一和第二侧壁栅极可以沿着中心栅电极的外侧形成在沟道区上。第一和第二存储节点可以形成在沟道区和侧壁栅电极之间。

24. 发明授权

US07187030B2 SONOS memory device 有权
标题翻译： SONOS存储设备
公开(公告)号：US07187030B2
公开(公告)日：2007-03-06
申请号：US10867706
申请日：2004-06-16
申请人： Soo-doo Chae , Chung-woo Kim , Jo-won Lee , Moon-kyung Kim
发明人： Soo-doo Chae , Chung-woo Kim , Jo-won Lee , Moon-kyung Kim
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0466
摘要： A SONOS memory device, and a method of erasing data from the same, includes injecting charge carriers of a second sign into a trapping film, which traps charge carriers of a first sign to store data therein. The charge carriers of the second sign are generated by an electric field formed between one of a first and second electrodes contacting at least one bit line and a gate electrode contacting a word line. A blocking film may be provided between the gate electrode and the trapping film. The charge carriers of the second sign may be hot holes. This erasing improves erasing speed, thereby improving performance of the SONOS memory device.
摘要翻译： SONOS存储器件和从其中擦除数据的方法包括将第二符号的电荷载体注入陷阱膜，捕获膜俘获第一符号的电荷载体以在其中存储数据。第二符号的电荷载体由形成在与至少一个位线接触的第一和第二电极中的一个与接触字线的栅电极之间的电场产生。可以在栅电极和捕获膜之间设置阻挡膜。第二标志的电荷载体可能是热孔。这种擦除提高了擦除速度，从而提高了SONOS存储器件的性能。

25. 发明授权

US07858464B2 Methods of manufacturing non-volatile memory devices having insulating layers treated using neutral beam irradiation 失效
标题翻译：制造具有使用中性束照射处理的绝缘层的非易失性存储器件的方法
公开(公告)号：US07858464B2
公开(公告)日：2010-12-28
申请号：US12346934
申请日：2008-12-31
申请人： Soo-doo Chae , Chung-woo Kim , Choong-man Lee , Yung-hee Lee , Chan-jin Park , Sung-wook Hwang , Jeong-hee Han , Do-haing Lee , Jin-seok Lee
发明人： Soo-doo Chae , Chung-woo Kim , Choong-man Lee , Yung-hee Lee , Chan-jin Park , Sung-wook Hwang , Jeong-hee Han , Do-haing Lee , Jin-seok Lee
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/31155 , H01L27/11568 , H01L29/66833 , H01L29/792
摘要： Methods of manufacturing non-volatile memory devices that can reduce or prevent loss of charges stored in a charge storage layer and/or that can improve charge storage capacity by neutral beam irradiation of an insulating layer are disclosed. The methods include forming a tunneling insulating layer on a substrate, forming a charge storage layer on the tunneling insulating layer, forming a blocking insulating layer on the charge storage layer, irradiating the blocking insulating layer and/or the tunneling insulating layer with a neutral beam, and forming a gate conductive layer on the blocking insulating layer.
摘要翻译：公开了制造可以减少或防止存储在电荷存储层中的电荷损失和/或可通过绝缘层的中性束照射改善电荷存储容量的非易失性存储器件的制造方法。所述方法包括在衬底上形成隧道绝缘层，在隧道绝缘层上形成电荷存储层，在电荷存储层上形成阻挡绝缘层，用中性光束照射阻挡绝缘层和/或隧道绝缘层并且在所述阻挡绝缘层上形成栅极导电层。

26. 发明授权

US07759196B2 Multi-bit non-volatile memory device, method of operating the same, and method of fabricating the same 失效
标题翻译：多位非易失性存储器件，其操作方法及其制造方法
公开(公告)号：US07759196B2
公开(公告)日：2010-07-20
申请号：US12209735
申请日：2008-09-12
申请人： Soo-doo Chae , Moon-kyung Kim , Jo-won Lee , Chung-woo Kim
发明人： Soo-doo Chae , Moon-kyung Kim , Jo-won Lee , Chung-woo Kim
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： G11C16/0475 , H01L21/28282 , H01L29/66833 , H01L29/7923
摘要： A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.
摘要翻译：可以提供多位非易失性存储器件及其操作和制造方法。存储器件可以包括形成在半导体衬底中的沟道区，以及与沟道区形成肖特基接触的源极和漏极。此外，中心栅电极可以位于沟道区的一部分上，并且第一和第二侧壁栅极可以沿着中心栅电极的外侧形成在沟道区上。第一和第二存储节点可以形成在沟道区和侧壁栅电极之间。

27. 发明授权

US07719871B2 Methods of operating and manufacturing logic device and semiconductor device including complementary nonvolatile memory device, and reading circuit for the same 有权
标题翻译：逻辑器件和半导体器件的操作和制造方法包括互补的非易失性存储器件和用于其的读取电路
公开(公告)号：US07719871B2
公开(公告)日：2010-05-18
申请号：US12025372
申请日：2008-02-04
申请人： Yoon-dong Park , Jo-won Lee , Chung-woo Kim , Eun-hong Lee , Sun-ae Seo , Woo-joo Kim , Hee-soon Chae , Soo-doo Chae , I-hun Song
发明人： Yoon-dong Park , Jo-won Lee , Chung-woo Kim , Eun-hong Lee , Sun-ae Seo , Woo-joo Kim , Hee-soon Chae , Soo-doo Chae , I-hun Song
IPC分类号： G11C5/06
CPC分类号： G11C11/5621 , H01L27/0688 , H01L27/11521 , H01L27/11551
摘要： Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.
摘要翻译：提供了一种互补的非易失性存储器件，其操作和制造方法，逻辑器件和具有该非易失性存储器件的半导体器件及其读取电路。互补非易失性存储器件包括顺序堆叠并具有互补关系的第一非易失性存储器和第二非易失性存储器。第一和第二非易失性存储器被布置成使得其上表面相邻。

28. 发明申请

US20080212376A1 METHODS OF OPERATING AND MANUFACTURING LOGIC DEVICE AND SEMICONDUCTOR DEVICE INCLUDING COMPLEMENTARY NONVOLATILE MEMORY DEVICE, AND READING CIRCUIT FOR THE SAME 有权
标题翻译：操作和制造逻辑器件和包括补充非易失性存储器件的半导体器件的方法及其读取电路
公开(公告)号：US20080212376A1
公开(公告)日：2008-09-04
申请号：US12025372
申请日：2008-02-04
申请人： Yoon-dong Park , Jo-won Lee , Chung-woo Kim , Eun-hong Lee , Sun-ae Seo , Woo-joo Kim , Hee-soon Chae , Soo-doo Chae , I-hun Song
发明人： Yoon-dong Park , Jo-won Lee , Chung-woo Kim , Eun-hong Lee , Sun-ae Seo , Woo-joo Kim , Hee-soon Chae , Soo-doo Chae , I-hun Song
IPC分类号： G11C16/06 , H01L21/336 , G11C7/00
CPC分类号： G11C11/5621 , H01L27/0688 , H01L27/11521 , H01L27/11551
摘要： Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.
摘要翻译：提供了一种互补的非易失性存储器件，其操作和制造方法，逻辑器件和具有该非易失性存储器件的半导体器件及其读取电路。互补非易失性存储器件包括顺序堆叠并具有互补关系的第一非易失性存储器和第二非易失性存储器。第一和第二非易失性存储器被布置成使得其上表面相邻。

29. 发明申请

US20060108629A1 Multi-bit non-volatile memory device, method of operating the same, and method of fabricating the same 审中-公开
标题翻译：多位非易失性存储器件，其操作方法及其制造方法
公开(公告)号：US20060108629A1
公开(公告)日：2006-05-25
申请号：US11220619
申请日：2005-09-08
申请人： Soo-doo Chae , Moon-kyung Kim , Jo-won Lee , Chung-woo Kim
发明人： Soo-doo Chae , Moon-kyung Kim , Jo-won Lee , Chung-woo Kim
IPC分类号： H01L29/788
CPC分类号： G11C16/0475 , H01L29/40117 , H01L29/66833 , H01L29/7923
摘要： A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.
摘要翻译：可以提供多位非易失性存储器件及其操作和制造方法。存储器件可以包括形成在半导体衬底中的沟道区，以及与沟道区形成肖特基接触的源极和漏极。此外，中心栅电极可以位于沟道区的一部分上，并且第一和第二侧壁栅极可以沿着中心栅电极的外侧形成在沟道区上。第一和第二存储节点可以形成在沟道区和侧壁栅电极之间。

30. 发明授权

US07349262B2 Methods of programming silicon oxide nitride oxide semiconductor (SONOS) memory devices 有权
标题翻译：氧化硅氧化物半导体（SONOS）存储器件的编程方法
公开(公告)号：US07349262B2
公开(公告)日：2008-03-25
申请号：US11432375
申请日：2006-05-12
申请人： Youn-seok Jeong , Chung-woo Kim , Hee-soon Chae , Ju-hyung Kim , Jeong-hee Han , Jae-woong Hyun
发明人： Youn-seok Jeong , Chung-woo Kim , Hee-soon Chae , Ju-hyung Kim , Jeong-hee Han , Jae-woong Hyun
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0466 , G11C16/04 , G11C29/50 , G11C29/50004
摘要： A method of programming a silicon oxide nitride oxide semiconductor (SONOS) memory device is provided. The SONOS memory device includes a substrate, first and second impurity regions spaced apart on the substrate, a gate oxide layer formed over the substrate between the first and second impurity regions, a trap layer formed over the gate oxide layer, an insulation layer formed over the trap layer, and a gate electrode formed over the insulation layer. The method of programming the SONOS device includes writing data into the SONOS memory device by applying a first voltage to the first impurity region, a gate voltage to the gate electrode, and a second voltage to the second impurity region, where the second voltage is a negative voltage.
摘要翻译：提供了一种编程氧化硅氮氧化物半导体（SONOS）存储器件的方法。 SONOS存储器件包括衬底，在衬底上间隔开的第一和第二杂质区，在第一和第二杂质区之间的衬底上形成的栅氧化层，在栅极氧化物层上形成的阱层，形成在绝缘层上的绝缘层陷阱层和形成在绝缘层上的栅电极。对SONOS设备进行编程的方法包括：通过向第一杂质区施加第一电压，向栅电极施加第一电压，向第二杂质区施加第二电压，将数据写入SONOS存储器件，其中第二电压为负电压。

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