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21. 发明申请

US20090230379A1 Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Memory Module 有权
标题翻译：集成电路，制造集成电路的方法和存储器模块
公开(公告)号：US20090230379A1
公开(公告)日：2009-09-17
申请号：US12047167
申请日：2008-03-12
申请人： Ulrich Klostermann , Rainer Leuschner
发明人： Ulrich Klostermann , Rainer Leuschner
IPC分类号： H01L45/00 , H01L21/762
CPC分类号： H01L43/08 , G11C11/15 , G11C11/1675
摘要： According to one embodiment of the present invention, an integrated circuit including a plurality of memory cells is provided. Each memory cell includes a resistivity changing memory element which includes a top electrode, a bottom electrode, and resistivity changing material being disposed between the top electrode and the bottom electrode. Each resistivity changing memory element is at least partially surrounded by a thermal insulating structure. The thermal insulating structures are arranged such that the dissipation of heat generated within the resistivity changing memory elements into the environment of the resistivity changing memory elements is lowered.
摘要翻译：根据本发明的一个实施例，提供了包括多个存储单元的集成电路。每个存储单元包括电阻率变化存储元件，其包括设置在顶部电极和底部电极之间的顶部电极，底部电极和电阻率变化材料。每个电阻率变化记忆元件至少部分地被绝热结构包围。热绝缘结构被布置成使得在电阻率变化的存储元件内产生的热量消耗到电阻率变化存储元件的环境中降低。

22. 发明申请

US20090218600A1 Memory Cell Layout 审中-公开
标题翻译：存储单元布局
公开(公告)号：US20090218600A1
公开(公告)日：2009-09-03
申请号：US12040227
申请日：2008-02-29
申请人： Human Park , Ulrich Klostermann
发明人： Human Park , Ulrich Klostermann
IPC分类号： H01L29/76 , H01L21/82 , G06F17/50
CPC分类号： G06F17/5068 , G11C2213/79 , H01L27/0207 , H01L27/222 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/065 , H01L45/085 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/149
摘要： A method for manufacturing an integrated circuit and an integrated circuit are described. In one embodiment, the method for manufacturing the integrated circuit includes determining a layout for numerous memory elements based on memory-specific parameters, and determining a layout for a front-end-of-line (FEOL) component of the integrated circuit based on electrical parameters. Once these two layouts are determined, the layouts are combined to produce a layout for a memory cell on the integrated circuit.
摘要翻译：对集成电路和集成电路的制造方法进行说明。在一个实施例中，用于制造集成电路的方法包括基于特定于存储器的参数确定多个存储器元件的布局，以及基于电气的方式确定集成电路的前端（FEOL）部件的布局参数。一旦确定了这两个布局，则将布局组合以产生集成电路上的存储器单元的布局。

23. 发明申请

US20090218559A1 Integrated Circuit, Memory Cell Array, Memory Module, and Method of Manufacturing an Integrated Circuit 审中-公开
标题翻译：集成电路，存储单元阵列，存储器模块和制造集成电路的方法
公开(公告)号：US20090218559A1
公开(公告)日：2009-09-03
申请号：US12040372
申请日：2008-02-29
申请人： Ulrich Klostermann
发明人： Ulrich Klostermann
IPC分类号： H01L45/00 , H01L21/768
CPC分类号： H01L27/228
摘要： According to one embodiment of the present invention, an integrated circuit is provided including a plurality of magneto-resistive memory cells. Each memory cell includes a magnetic tunneling junction stack, wherein the top surfaces of the magnetic tunneling junctions stacks are electrically connected to a common continuous conductive plate.
摘要翻译：根据本发明的一个实施例，提供了包括多个磁阻存储器单元的集成电路。每个存储单元包括磁隧道结叠层，其中磁隧道结叠层的顶表面电连接到公共的连续导电板。

24. 发明申请

US20080080109A1 Electric device protection circuit and method for protecting an electric device 失效
标题翻译：电气设备保护电路及其保护方法
公开(公告)号：US20080080109A1
公开(公告)日：2008-04-03
申请号：US11541402
申请日：2006-09-29
申请人： Alexander Duch , Ulrich Klostermann , Michael Kund
发明人： Alexander Duch , Ulrich Klostermann , Michael Kund
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , G11C13/0011 , G11C13/0038 , G11C13/0059 , H02H9/02
摘要： An electric device protection circuit comprises at least one conductive bridging unit which electrically connects a terminal of the electric device to a protection node set to a protection potential, the protection potential being chosen such that the conductive bridging unit switches from a resistive state to a conductive state in case that the voltage or current at the terminal exceeds a predetermined threshold value.
摘要翻译：电气设备保护电路包括至少一个导电桥接单元，其将电气设备的端子与设置为保护电位的保护节点电连接，所述保护电位被选择为使得导电桥接单元从电阻状态切换到导电在端子处的电压或电流超过预定阈值的情况下状态。

25. 发明申请

US20070297219A1 Magnetoresistive memory cell, methods of programming a magnetoresistive memory cell and methods of reading a magnetoresistive memory cell 有权
标题翻译：磁阻存储单元，磁阻存储单元的编程方法以及读磁阻存储单元的方法
公开(公告)号：US20070297219A1
公开(公告)日：2007-12-27
申请号：US11473531
申请日：2006-06-23
申请人： Rok Dittrich , Ulrich Klostermann
发明人： Rok Dittrich , Ulrich Klostermann
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/5607
摘要： A magnetoresistive memory cell has a magnetic stack providing an effective anisotropy field of a storage layer of the magnetic stack during thermal select heating, at least one line providing at least one external magnetic field to the magnetic stack, the effective anisotropy field and the at least one external magnetic field having a non-zero angle relative to one another.
摘要翻译：磁阻存储单元具有磁堆栈，其在热选择加热期间提供磁堆栈的存储层的有效各向异性场，至少一行向磁堆提供至少一个外部磁场，有效各向异性场和至少一个外部磁场相对于彼此具有非零角度。

26. 发明授权

US07205596B2 Adiabatic rotational switching memory element including a ferromagnetic decoupling layer 失效
标题翻译：绝热旋转开关存储元件，包括铁磁去耦层
公开(公告)号：US07205596B2
公开(公告)日：2007-04-17
申请号：US11117713
申请日：2005-04-29
申请人： Ulrich Klostermann , Peter Beer , Manfred Ruehrig
发明人： Ulrich Klostermann , Peter Beer , Manfred Ruehrig
IPC分类号： H01L29/76
CPC分类号： H01L43/08 , H01F10/30 , H01F10/3254 , H01F10/3272 , H01F10/3295
摘要： A magnetoresistive memory element includes a stacked structure with a ferromagnetic reference region including a fixed magnetization; a ferromagnetic free region including a free magnetization that is free to be switched between oppositely aligned directions with respect to an easy axis thereof; and a tunneling barrier made of a non-magnetic material. The ferromagnetic reference and free regions and the tunneling barrier together form a magnetoresistive tunneling junction. The ferromagnetic free region includes a plurality of N ferromagnetic free layers being magnetically coupled such that magnetizations of adjacent ferromagnetic free layers are in antiparallel alignment, where N is an integer greater than or equal to two. The ferromagnetic free region further includes at least one ferromagnetic decoupling layer including frustrated magnetization in orthogonal alignment to ferromagnetic free layer magnetizations and being arranged in between adjacent ferromagnetic free layers.
摘要翻译：磁阻存储元件包括具有包括固定磁化强度的铁磁参考区的堆叠结构; 铁磁自由区域，包括相对于其容易轴线在相对排列的方向之间自由切换的自由磁化; 以及由非磁性材料制成的隧道屏障。铁磁参考和自由区和隧道势垒一起形成磁阻隧道结。铁磁自由区包括磁耦合的多个N个铁磁自由层，使得相邻铁磁自由层的磁化反平行对准，其中N是大于或等于2的整数。铁磁自由区还包括至少一个铁磁解耦层，其包括与铁磁自由层磁化正交对准的失效磁化，并布置在相邻的铁磁自由层之间。

27. 发明申请

US20070069296A1 High-density high current device cell 审中-公开
标题翻译：高密度大电流器件电池
公开(公告)号：US20070069296A1
公开(公告)日：2007-03-29
申请号：US11369194
申请日：2006-03-06
申请人： Human Park , Rainer Leuschner , Ulrich Klostermann , Richard Ferrant
发明人： Human Park , Rainer Leuschner , Ulrich Klostermann , Richard Ferrant
IPC分类号： H01L27/12
CPC分类号： H01L27/228 , B82Y10/00
摘要： A cell design and methods for reducing the cell size of cells in high-current devices, such as MRAM, by increasing the effective width of a transistor in the cell to be greater than the actual width of the active area of the cell are described. This permits the cell size to be decreased without decreasing the current that is driven by the transistor. According to the invention, this is achieved by increasing the length of gate portions of one or more transistors within the active area of a cell to increase the effective transistor width. In one embodiment, two transistors, electrically connected in parallel, are used per cell. The two transistors double the effective transistor width within the cell relative to a single transistor design. Such cell designs can be used with a variety of devices, including various types of MRAM and PCRAM.
摘要翻译：描述了通过将电池中的晶体管的有效宽度增加到大于电池的有效面积的实际宽度来减小大电流器件（例如MRAM）中的电池单元尺寸的电池设计和方法。这允许在不降低由晶体管驱动的电流的情况下降低电池尺寸。根据本发明，这通过增加单元的有效区域内的一个或多个晶体管的栅极部分的长度来增加有效晶体管宽度来实现。在一个实施例中，每个单元使用并联电连接的两个晶体管。两个晶体管相对于单晶体管设计，使单元内的有效晶体管宽度倍增。这样的单元设计可以与各种设备一起使用，包括各种类型的MRAM和PCRAM。

28. 发明申请

US20060171197A1 Magnetoresistive memory element having a stacked structure 审中-公开
标题翻译：具有堆叠结构的磁阻存储元件
公开(公告)号：US20060171197A1
公开(公告)日：2006-08-03
申请号：US11045512
申请日：2005-01-31
申请人： Ulrich Klostermann , Daniel Braun
发明人： Ulrich Klostermann , Daniel Braun
IPC分类号： G11C11/00
CPC分类号： B82Y25/00 , G11C11/15 , H01F10/3254 , H01F10/3272 , H01L43/08
摘要： A magnetoresistive memory element has a stacked structure including: a tunneling barrier made of non-magnetic material, a first magnetic system with a ferromagnetic tunneling junction reference layer barrier having a fixed magnetic moment vector on one side of the tunneling adjacent to the non-magnetic material, and a second magnetic system with a ferromagnetic tunneling junction free layer on an opposite side of the tunneling barrier having a free magnetic moment vector adjacent to the non-magnetic material and forming a magnetoresistive tunneling junction. The tunneling junction free layer is one of a plurality of N ferromagnetic free layers which are antiferromagnetically coupled. The first magnetic system is sandwiched in between the tunneling junction free layer and at least one of the ferromagnetic free layers that are anti-ferromagnetically coupled therewith.
摘要翻译：磁阻存储元件具有堆叠结构，其包括：由非磁性材料制成的隧道势垒，具有铁磁隧道结参考层势垒的第一磁系统，在与非磁性相邻的隧道的一侧具有固定的磁矩矢量材料和具有在隧道势垒的相对侧上的铁磁隧道结自由层的第二磁系统，其具有与非磁性材料相邻的自由磁矩矢量并形成磁阻隧道结。隧道结自由层是反铁磁耦合的多个N铁磁自由层之一。第一磁系统被夹在隧道结自由层和与其铁磁耦合的铁磁自由层中的至少一个之间。

29. 发明授权

US07075807B2 Magnetic memory with static magnetic offset field 失效
标题翻译：具有静磁场的磁记忆体
公开(公告)号：US07075807B2
公开(公告)日：2006-07-11
申请号：US10920562
申请日：2004-08-18
申请人： Rainer Leuschner , Daniel Braun , Gill Yong Lee , Ulrich Klostermann
发明人： Rainer Leuschner , Daniel Braun , Gill Yong Lee , Ulrich Klostermann
IPC分类号： H01L29/82
CPC分类号： H01L27/222 , G11C11/16 , H01L43/08
摘要： A magnetoresistive or magnetic memory element and a magnetic random access memory having one or more magnetic memory elements. The memory element includes a magnetic tunnel junction including first and a second magnetic layers. The first magnetic layer having a free magnetization. The free magnetization of the first magnetic layer is magnetically coupled to a first current line and a second current line for switching the free magnetization, and a mechanism for applying a static magnetic offset field in the direction of at least one of the first and second current lines.
摘要翻译：磁阻或磁存储元件和具有一个或多个磁存储元件的磁随机存取存储器。存储元件包括包含第一和第二磁性层的磁性隧道结。第一磁性层具有自由磁化。第一磁性层的自由磁化磁耦合到第一电流线和用于切换自由磁化的第二电流线，以及用于在第一和第二电流中的至少一个方向上施加静态磁偏移场的机构线条。

30. 发明申请

US20050254180A1 MAGNETIC TUNNEL JUNCTION CAP STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：磁性隧道结结构及其形成方法
公开(公告)号：US20050254180A1
公开(公告)日：2005-11-17
申请号：US10709573
申请日：2004-05-14
申请人： Sivananda Kanakasabapathy , David Abraham , Ulrich Klostermann
发明人： Sivananda Kanakasabapathy , David Abraham , Ulrich Klostermann
IPC分类号： G11B5/33 , H01L43/12
CPC分类号： H01L43/12
摘要： A a magnetic random access memory (MRAM) device includes a cap layer formed over a magnetic tunnel junction (MTJ) stack layer, an etch stop layer formed over the first cap layer, and a hardmask layer formed over the etch stop layer. The etch stop layer is selected from a material such that an etch chemistry used for removing the hardmask layer has selectivity against etching the etch stop layer material.
摘要翻译：磁性随机存取存储器（MRAM）器件包括形成在磁隧道结（MTJ）堆叠层上的覆盖层，形成在第一覆盖层上的蚀刻停止层，以及形成在蚀刻停止层上的硬掩模层。蚀刻停止层选自材料，使得用于去除硬掩模层的蚀刻化学性质对蚀刻停止层材料的蚀刻具有选择性。

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