专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07380107B2 Multi-processor system utilizing concurrent speculative source request and system source request in response to cache miss 失效
标题翻译：多处理器系统利用并发推测源请求和响应高速缓存未命中的系统源请求
公开(公告)号：US07380107B2
公开(公告)日：2008-05-27
申请号：US10756640
申请日：2004-01-13
申请人： Simon C. Steely, Jr. , Gregory Edward Tierney , Stephen R. Van Doren
发明人： Simon C. Steely, Jr. , Gregory Edward Tierney , Stephen R. Van Doren
IPC分类号： G06F15/00
CPC分类号： G06F9/383
摘要： Multi-processor systems and methods are disclosed that employ speculative source requests to obtain speculative data fills in response to a cache miss. In one embodiment, a source processor generates a speculative source request and a system source request in response to a cache miss. At least one processor provides a speculative data fill to a source processor in response to the speculative source request. The processor system provides a coherent data fill to the processor in response to the system source request.
摘要翻译：公开了多处理器系统和方法，其采用推测源请求以响应于高速缓存未命中来获得推测数据填充。在一个实施例中，源处理器响应于高速缓存未命中而产生推测源请求和系统源请求。响应于推测源请求，至少一个处理器向源处理器提供推测数据填充。处理器系统响应于系统源请求向处理器提供相干数据填充。

22. 发明授权

US07149852B2 System and method for blocking data responses 失效
标题翻译：用于阻止数据响应的系统和方法
公开(公告)号：US07149852B2
公开(公告)日：2006-12-12
申请号：US10761034
申请日：2004-01-20
申请人： Stephen R. Van Doren , Gregory Edward Tierney , Simon C. Steely, Jr.
发明人： Stephen R. Van Doren , Gregory Edward Tierney , Simon C. Steely, Jr.
IPC分类号： G06F12/00
CPC分类号： G06F12/0833 , G06F12/0817 , G06F12/0831 , G06F2212/1024 , G06F2212/1044
摘要： Systems and methods are disclosed for blocking data responses. One system includes a target node that, in response to a source broadcast request for requested data, provides a response that includes a copy of the requested data. The target node also provides a blocking message to a home node associated with the requested data. The blocking message being operative cause the home node to provide a non-data response to the source broadcast request if the blocking message is matched with the source broadcast request at the home node.
摘要翻译：公开了用于阻止数据响应的系统和方法。一个系统包括目标节点，其响应于所请求数据的源广播请求提供包括所请求数据的副本的响应。目标节点还向与请求的数据相关联的家庭节点提供阻塞消息。如果阻塞消息与归属节点处的源广播请求匹配，则阻塞消息正在起作用，导致归属节点向源广播请求提供非数据响应。

23. 发明授权

US06636948B2 Method and system for a processor to gain assured ownership of an up-to-date copy of data 失效
标题翻译：一种处理器的方法和系统，以获得对数据的最新副本的有保证的所有权
公开(公告)号：US06636948B2
公开(公告)日：2003-10-21
申请号：US09834551
申请日：2001-04-13
申请人： Simon C. Steely, Jr. , Stephen R. Van Doren , Madhu Sharna
发明人： Simon C. Steely, Jr. , Stephen R. Van Doren , Madhu Sharna
IPC分类号： G06F1200
CPC分类号： G06F12/0817
摘要： A performance enhancing change-to-dirty operation (CTD) is disclosed wherein contention among several processors trying to gain ownership of a block of data is obviated by arranging the CTD to always succeed. A method and a system are disclosed where a processor in a multiprocessor system having a copy of data gains assured ownership of data that the processor may then write. The method provides for the possibilities of conditions that may exist and provides a scenario that the requesting processor may have to wait for the ownership. Conditions are handled where the memory is the “owner” of the data and where other processor are requesting ownership, and where copies of the data exist at other processors. The method provides for messages to other processor having copies of the data informing them that the data is now invalid.
摘要翻译：公开了一种性能提升的改变到脏操作（CTD），其中通过使CTD总是成功地排除尝试获得数据块所有权的若干处理器中的争用。公开了一种方法和系统，其中具有数据副本的多处理器系统中的处理器确保处理器然后可以写入的数据的所有权。该方法提供可能存在的条件的可能性并提供请求处理器可能必须等待所有权的情况。在内存是数据的“所有者”以及其他处理器请求所有权的情况下以及数据的副本存在于其他处理器的情况下处理条件。该方法向具有数据副本的其他处理器提供消息，通知他们数据现在无效。

24. 发明授权

US06961825B2 Cache coherency mechanism using arbitration masks 有权
标题翻译：使用仲裁掩码的缓存一致性机制
公开(公告)号：US06961825B2
公开(公告)日：2005-11-01
申请号：US09768418
申请日：2001-01-24
申请人： Simon C. Steely, Jr. , Stephen Van Doren , Madhumitra Sharma
发明人： Simon C. Steely, Jr. , Stephen Van Doren , Madhumitra Sharma
IPC分类号： G06F12/08 , H04L29/08 , G06F12/00
CPC分类号： H04L67/2804 , G06F12/0824 , G06F12/0826 , H04L67/2852 , H04L69/329
摘要： A distributed processing system includes a cache coherency mechanism that essentially encodes network routing information into sectored presence bits. The mechanism organizes the sectored presence bits as one or more arbitration masks that system switches decode and use directly to route invalidate messages through one or more higher levels of the system. The lower level or levels of the system use local routing mechanisms, such as local directories, to direct the invalidate messages to the individual processors that are holding the data of interest.
摘要翻译：分布式处理系统包括高速缓存一致性机制，其基本上将网络路由信息编码为扇区存在位。该机制将分区存在位组织为一个或多个仲裁掩码，系统交换机直接解码并使用，以通过系统的一个或多个更高级别路由无效消息。系统的较低级别或级别使用本地路由机制（如本地目录）将无效消息引导到保存感兴趣的数据的各个处理器。

25. 发明授权

US06249520B1 High-performance non-blocking switch with multiple channel ordering constraints 失效
标题翻译：具有多通道排序限制的高性能非阻塞开关
公开(公告)号：US06249520B1
公开(公告)日：2001-06-19
申请号：US08957664
申请日：1997-10-24
申请人： Simon C. Steely, Jr. , Stephen R. VanDoren , Madhumitra Sharma , Craig D. Keefer , David W. Davis
发明人： Simon C. Steely, Jr. , Stephen R. VanDoren , Madhumitra Sharma , Craig D. Keefer , David W. Davis
IPC分类号： H04L1250
CPC分类号： G06F13/4022 , G06F12/0826 , G06F15/17393
摘要： An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.
摘要翻译：用于大SMP计算机系统的架构和一致性协议包括分层交换结构，其允许多个多处理器节点耦合到交换机以以最佳性能进行操作。在每个多处理器节点内，提供同时缓冲系统，其允许多处理器节点的所有处理器以最高性能运行。存储器在节点之间共享，存储器的一部分驻留在每个多处理器节点处。每个多处理器节点包括用于维持存储器一致性的多个元件，包括受害缓存，目录和事务跟踪表。受害者缓存允许选择性地更新目的地存储在远程多处理节点处的存储器的受害者数据，从而提高存储器的整体性能。通过在每个存储器处包括延迟的写入缓冲器来进一步改善存储器性能，该缓冲器与目录一起使用以识别要写入存储器的受害者。耦合到每个节点的目录的输出的arb总线为通过SMP传输的所有消息提供了中心排序点。消息包括多个事务，并且根据消息的处理阶段，将每个事务分配给多个不同的虚拟通道。因此，通过提供用于维护系统顺序的简单方法，使用虚拟通道有助于维持数据一致性。使用虚拟通道和目录结构，可以避免先前导致死锁的高速缓存一致性问题。

26. 发明授权

US06202126B1 Victimization of clean data blocks 失效
标题翻译：干净数据块的受害
公开(公告)号：US06202126B1
公开(公告)日：2001-03-13
申请号：US08957697
申请日：1997-10-24
申请人： Stephen Van Doren , Simon C. Steely, Jr. , Madhumitra Sharma
发明人： Stephen Van Doren , Simon C. Steely, Jr. , Madhumitra Sharma
IPC分类号： G06F1200
CPC分类号： G06F12/0804 , G06F12/0833
摘要： A method for preventing inadvertent invalidation of data elements in a system having a separate probe queue and fill queue for each central processing unit, is provided wherein a central processing unit stores a clean data element, that would otherwise have been discarded, in a victim data buffer when it is evicted from cache. The central processing unit subsequently issues a clean-victim command to the system control logic when the readmiss or read-miss-modify command, targeting the data element that maps to the same location in cache as the clean data element, is issued. The clean-victim command causes the duplicate tag store to indicate that the clean data element is no longer stored in that central processing unit's cache. While the data is stored therein, the central processing unit cannot issue a probe message that targets that data until the victim data buffer has been deallocated. The central processing unit cannot modify the data element and therefore, if a probe invalidate has previously been issued for the clean version of the data element, it will not be able to inadvertently invalidate a modified version of the data element.
摘要翻译：提供了一种用于防止在具有用于每个中央处理单元的单独的探测队列和填充队列的系统中的数据元素的无意的无效的方法，其中中央处理单元将干脆的数据元素（否则将被丢弃）存储在受害者数据中缓冲区从缓存中逐出。当发出针对映射到与清洁数据元素在高速缓存中的相同位置的数据元素的readmiss或read-miss-modify命令时，中央处理单元随后向系统控制逻辑发出清理受害者命令。 clean-victim命令使重复的标签存储指示干净的数据元素不再存储在该中央处理器的缓存中。当数据存储在其中时，中央处理单元不能发出针对该数据的探测消息，直到受害者数据缓冲器被释放。中央处理单元不能修改数据元素，因此如果先前为数据元素的干净版本发出了探针无效，则它将无法无意中使数据元素的修改版本无效。

27. 发明授权

US09588889B2 Domain state 有权
标题翻译：域状态
公开(公告)号：US09588889B2
公开(公告)日：2017-03-07
申请号：US13995991
申请日：2011-12-29
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0802 , G06F12/0811 , G06F12/0817 , G06F13/00
摘要： Method and apparatus to efficiently maintain cache coherency by reading/writing a domain state field associated with a tag entry within a cache tag directory. A value may be assigned to a domain state field of a tag entry in a cache tag directory. The cache tag directory may belong to a hierarchy of cache tag directories. Each tag entry may be associated with a cache line from a cache belonging to a first domain. The first domain may contain multiple caches. The value of the domain state field may indicate whether its associated cache line can be read or changed.
摘要翻译：通过读/写与缓存标签目录中的标签条目相关联的域状态字段来有效地维持高速缓存一致性的方法和装置。可以将值分配给缓存标签目录中的标签条目的域状态字段。缓存标签目录可能属于高速缓存标签目录的层次结构。每个标签条目可以与来自属于第一域的高速缓存行相关联。第一个域可能包含多个缓存。域状态字段的值可以指示其相关联的高速缓存行是否可以被读取或改变。

28. 发明授权

US09201792B2 Short circuit of probes in a chain 有权
标题翻译：探针在链中短路
公开(公告)号：US09201792B2
公开(公告)日：2015-12-01
申请号：US13996012
申请日：2011-12-29
申请人： Simon C. Steely, Jr. , Samantika Subramaniam , William C. Hasenplaugh , Joel S. Emer
发明人： Simon C. Steely, Jr. , Samantika Subramaniam , William C. Hasenplaugh , Joel S. Emer
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/082
摘要： A multi-core processing apparatus may provide a cache probe and data retrieval method. The method may comprise sending a memory request from a requester to a record keeping structure. The memory request may have a memory address of a memory that stores requested data. The method may further comprise determining that a local last accessor of the memory address may have a copy of the requested data up to date with the memory. The local last accessor may be within a local domain that the requester belongs to. The method may further comprise sending a cache probe to the local last accessor and retrieving a latest value of the requested data from the local last accessor to the requester.
摘要翻译：多核处理装置可以提供高速缓存探针和数据检索方法。该方法可以包括将请求者的存储器请求发送到记录保存结构。存储器请求可以具有存储请求的数据的存储器的存储器地址。该方法还可以包括确定存储器地址的本地最后访问器可以具有与存储器一起的所请求数据的副本。本地最后一个访问者可能在请求者所属的本地域内。该方法还可以包括向本地最后一个访问器发送高速缓存探测器，并且从本地最后一个访问器检索所请求的数据的最新值到请求者。

29. 发明授权

US08438335B2 Probe speculative address file 失效
标题翻译：探测推测地址文件
公开(公告)号：US08438335B2
公开(公告)日：2013-05-07
申请号：US12892476
申请日：2010-09-28
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F2212/507
摘要： An apparatus to resolve cache coherency is presented. In one embodiment, the apparatus includes a microprocessor comprising one or more processing cores. The apparatus also includes a probe speculative address file unit, coupled to a cache memory, comprising a plurality of entries. Each entry includes a timer and a tag associated with a memory line. The apparatus further includes control logic to determine whether to service an incoming probe based at least in part on a timer value.
摘要翻译：提出了一种解决高速缓存一致性的设备。在一个实施例中，该装置包括具有一个或多个处理核心的微处理器。该装置还包括耦合到高速缓冲存储器的探测推测地址文件单元，包括多个条目。每个条目包括定时器和与存储器线相关联的标签。该装置还包括至少部分地基于定时器值来确定是否对入站探测器进行服务的控制逻辑。

30. 发明授权

US08407421B2 Cache spill management techniques using cache spill prediction 失效
标题翻译：缓存溢出管理技术使用缓存溢出预测
公开(公告)号：US08407421B2
公开(公告)日：2013-03-26
申请号：US12639214
申请日：2009-12-16
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh , Aamer Jaleel , George Z. Chrysos
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh , Aamer Jaleel , George Z. Chrysos
IPC分类号： G06F12/00
CPC分类号： G06F12/0806 , G06F12/12
摘要： An apparatus and method is described herein for intelligently spilling cache lines. Usefulness of cache lines previously spilled from a source cache is learned, such that later evictions of useful cache lines from a source cache are intelligently selected for spill. Furthermore, another learning mechanism—cache spill prediction—may be implemented separately or in conjunction with usefulness prediction. The cache spill prediction is capable of learning the effectiveness of remote caches at holding spilled cache lines for the source cache. As a result, cache lines are capable of being intelligently selected for spill and intelligently distributed among remote caches based on the effectiveness of each remote cache in holding spilled cache lines for the source cache.
摘要翻译：这里描述了用于智能地溢出高速缓存行的装置和方法。了解先前从源缓存溢出的高速缓存行的有用性，从而智能地选择来自源缓存的随后驱逐的溢出。此外，另一种学习机制 - 缓存溢出预测 - 可以单独实施或结合有用性预测来实现。高速缓存溢出预测能够学习在为源缓存保留溢出的高速缓存行时远程高速缓存的有效性。因此，基于每个远程高速缓存在保存用于源高速缓存的溢出高速缓存行的有效性的情况下，高速缓存行能够被智能地选择为溢出并且智能地分布在远程高速缓存中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式