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21. 发明授权

US08130608B2 Coupled ring oscillator and method for initializing the same 有权
标题翻译：耦合环形振荡器及其初始化方法
公开(公告)号：US08130608B2
公开(公告)日：2012-03-06
申请号：US12967498
申请日：2010-12-14
申请人： Akinori Matsumoto , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga , Takashi Morie
发明人： Akinori Matsumoto , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga , Takashi Morie
IPC分类号： G11B7/00 , H03K3/03
CPC分类号： H03K3/0315 , H03K2005/00052
摘要： In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.
摘要翻译：在包括q个环形振荡器的耦合环形振荡器中，每个环形振荡器包括连接在一起以形成环形的p个反相器电路，以及包括（p×q）个相位耦合电路的相位耦合环，每个相位耦合电路被配置为耦合p的一个的输出 q环振荡器中的一个的逆变器电路以预定的相位关系连接到另一个q个环形振荡器的p个反相器电路之一的输出，并且连接在一起以形成环形，用于至少一个组每个q环振荡器中的p个反相器电路中的一个的上升，属于至少一个组的q个反相器电路的输出彼此相位固定，使q个环形振荡器在同相中振荡固定状态，然后将q个逆变器电路的输出从同相固定状态解除。

22. 发明授权

US08013650B2 Phase adjustment circuit 有权
标题翻译：相位调整电路
公开(公告)号：US08013650B2
公开(公告)日：2011-09-06
申请号：US11514151
申请日：2006-09-01
申请人： Shiro Dosho , Shiro Sakiyama , Yusuke Tokunaga , Seiji Watanabe , Hiroshi Koshida
发明人： Shiro Dosho , Shiro Sakiyama , Yusuke Tokunaga , Seiji Watanabe , Hiroshi Koshida
IPC分类号： H03H11/16
CPC分类号： H03K5/13 , H03K5/15013 , H03K2005/00052 , H03K2005/00273
摘要： A phase adjustment circuit includes first to nth two-phase adjustment circuits. Each two-phase adjustment circuit includes a first logic circuit for performing logical sum of two input signals, a second logic circuit for performing logical product of the two input signals, a first delay circuit having a signal delay equal to that of the second logic circuit and configured to delay a signal output from the first logic circuit, and a second delay circuit having a signal delay equal to that of the first logic circuit and configured to delay a signal output from the second logic circuit. Two signals output from two of the two-phase adjustment circuits in a certain stage are input into one of the two-phase adjustment circuits in the next stage.
摘要翻译：相位调整电路包括第一至第二相位调整电路。每个两相调节电路包括用于执行两个输入信号的逻辑和的第一逻辑电路，用于执行两个输入信号的逻辑积的第二逻辑电路，具有等于第二逻辑电路的信号延迟的信号延迟的第一延迟电路并且被配置为延迟从第一逻辑电路输出的信号;以及第二延迟电路，其具有等于第一逻辑电路的信号延迟的信号延迟，并且被配置为延迟从第二逻辑电路输出的信号。在一定阶段从两相调节电路中输出的两个信号在下一级输入到两相调节电路之一。

23. 发明申请

US20110080821A1 COUPLED RING OSCILLATOR AND METHOD FOR INITIALIZING THE SAME 有权
标题翻译：耦合振荡器及其初始化方法
公开(公告)号：US20110080821A1
公开(公告)日：2011-04-07
申请号：US12967498
申请日：2010-12-14
申请人： Akinori Matsumoto , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga , Takashi Morie
发明人： Akinori Matsumoto , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga , Takashi Morie
IPC分类号： G11B20/10 , H03K3/03
CPC分类号： H03K3/0315 , H03K2005/00052
摘要： In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.
摘要翻译：在包括q个环形振荡器的耦合环形振荡器中，每个环形振荡器包括连接在一起以形成环形的p个反相器电路，以及包括（p×q）个相位耦合电路的相位耦合环，每个相位耦合电路被配置为耦合p的一个的输出 q环振荡器中的一个的逆变器电路以预定的相位关系连接到另一个q个环形振荡器的p个反相器电路之一的输出，并且连接在一起以形成环形，用于至少一个组每个q环振荡器中的p个反相器电路中的一个的上升，属于至少一个组的q个反相器电路的输出彼此相位固定，使q个环形振荡器在同相中振荡固定状态，然后将q个逆变器电路的输出从同相固定状态解除。

24. 发明授权

US07782112B2 Device and method for generating clock signal 有权
标题翻译：用于产生时钟信号的装置和方法
公开(公告)号：US07782112B2
公开(公告)日：2010-08-24
申请号：US12330947
申请日：2008-12-09
申请人： Yusuke Tokunaga , Shiro Sakiyama , Shiro Dosho , Akinori Matsumoto
发明人： Yusuke Tokunaga , Shiro Sakiyama , Shiro Dosho , Akinori Matsumoto
IPC分类号： G06F1/04
CPC分类号： H03K5/135 , H03K5/1565 , H03K23/54 , H03K2005/00241
摘要： In a device for generating a clock signal having a desired phase from input multi-phase clock signals, an intermediate clock generator generates, by using one of the input multi-phase clock signals as a reference clock signal, multi-phase intermediate clock signals in which one cycle is equal to a plurality of cycles of the reference clock signal. A first phase selector selects one of the multi-phase intermediate clock signals. A second phase selector selects one of the multi-phase clock signals. A latch circuit latches the intermediate clock signal selected by the first phase selector with the clock signal selected by the second phase selector.
摘要翻译：在用于从输入多相时钟信号产生期望相位的时钟信号的装置中，中间时钟发生器通过使用输入多相时钟信号之一作为参考时钟信号来产生多相中间时钟信号哪个周期等于参考时钟信号的多个周期。第一相位选择器选择多相中间时钟信号之一。第二相位选择器选择多相时钟信号之一。锁存电路将由第一相位选择器选择的中间时钟信号与由第二相位选择器选择的时钟信号进行锁存。

25. 发明申请

US20090237281A1 A/D CONVERTER 失效
标题翻译： A / D转换器
公开(公告)号：US20090237281A1
公开(公告)日：2009-09-24
申请号：US12093252
申请日：2007-07-30
申请人： Shiro Dosho , Takashi Morie , Yusuke Tokunaga , Shiro Sakiyama
发明人： Shiro Dosho , Takashi Morie , Yusuke Tokunaga , Shiro Sakiyama
IPC分类号： H03M1/12 , H03M1/00
CPC分类号： H03M1/123 , H03M1/1215 , H03M1/56
摘要： An A/D converter includes: a plurality of A/D conversion circuits (10a, 10b); an input selection section (20) for selecting the A/D conversion circuit that is not executing A/D conversion to supply analog amounts obtained by sample-holding an input signal; and an output selection section (30) for selecting the A/D conversion circuit that is not executing A/D conversion to output digital amounts obtained from the selected one. Each A/D conversion circuit includes: an input memory portion (11) for sequentially storing the supplied analog amounts in a plurality of analog memory elements (111); an A/D conversion portion (12) having a plurality of A/D conversion elements (121) for converting the analog amounts stored in the analog memory elements to digital amounts; and a shift output portion (13), having a plurality of registers (131) receiving the digital amounts from the A/D conversion elements to hold the digital amounts, for shifting and outputting the digital amounts held in the registers.
摘要翻译： A / D转换器包括：多个A / D转换电路（10a，10b）; 输入选择部分（20），用于选择不执行A / D转换的A / D转换电路以提供通过采样保持输入信号获得的模拟量; 以及用于选择不执行A / D转换的A / D转换电路以输出从所选择的数字量获得的数字量的输出选择部分（30）。每个A / D转换电路包括：用于在多个模拟存储器元件（111）中顺序地存储所提供的模拟量的输入存储器部分（11）。具有用于将存储在模拟存储器元件中的模拟量转换为数字量的多个A / D转换元件的A / D转换部分（12）以及移位输出部分（13），具有从A / D转换元件接收数字量以保持数字量的多个寄存器（131），用于移位和输出保存在寄存器中的数字量。

26. 发明申请

US20050077955A1 Low-pass filter for a pll, phase-locked loop and semiconductor integrated circuit 失效
标题翻译：低通滤波器，用于pll，锁相环和半导体集成电路
公开(公告)号：US20050077955A1
公开(公告)日：2005-04-14
申请号：US10500875
申请日：2003-05-22
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
IPC分类号： H03H11/12 , H03H11/04 , H03L7/08 , H03L7/081 , H03L7/089 , H03L7/093 , H03L7/107 , H03B1/00
CPC分类号： H03L7/0812 , H03L7/0891 , H03L7/0893 , H03L7/0896 , H03L7/093
摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.
摘要翻译：本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311）电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。

27. 发明授权

US07030688B2 Low-pass filter for a PLL, phase-locked loop and semiconductor integrated circuit 失效
标题翻译：用于PLL，锁相环和半导体集成电路的低通滤波器
公开(公告)号：US07030688B2
公开(公告)日：2006-04-18
申请号：US10500875
申请日：2003-05-22
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
IPC分类号： H03K5/00
CPC分类号： H03L7/0812 , H03L7/0891 , H03L7/0893 , H03L7/0896 , H03L7/093
摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.
摘要翻译：本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311）电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。

28. 发明授权

US07009426B2 Data transmission/reception system 失效
标题翻译：数据发送/接收系统
公开(公告)号：US07009426B2
公开(公告)日：2006-03-07
申请号：US10513965
申请日：2003-08-27
申请人： Shiro Dosho , Yusuke Tokunaga , Yasuyuki Doi , Hirofumi Nakagawa , Yoshito Date , Tetsuro Ohmori , Kaori Nishikawa
发明人： Shiro Dosho , Yusuke Tokunaga , Yasuyuki Doi , Hirofumi Nakagawa , Yoshito Date , Tetsuro Ohmori , Kaori Nishikawa
IPC分类号： H03K19/00
CPC分类号： G09G3/3685 , G09G2310/027 , G09G2330/06 , H04L25/0272 , H04L25/4902
摘要： In the process of transferring a clock signal and a plurality of data signals which are in synchronization with the clock signal, a driving pulse width of a driver switch is feedback-controlled by a clock transmission system (12), whereby the clock signal is transmitted at a small amplitude. A control signal having the pulse width is used for controlling the driver switch in each data transmission system (13), whereby transfer of each data signal at a small amplitude is realized at the same time. Further, in a clock reception system (10), the control signal having the pulse width is used in delay control of a clock delay circuit, whereby an optimum latch timing of received data in each data reception system (11) is realized.
摘要翻译：在传送与时钟信号同步的时钟信号和多个数据信号的过程中，驱动器开关的驱动脉冲宽度由时钟传输系统（12）进行反馈控制，从而传输时钟信号在一个小幅度。具有脉冲宽度的控制信号用于控制每个数据传输系统（13）中的驱动器开关，从而同时实现以小幅度传送每个数据信号。此外，在时钟接收系统（10）中，具有脉冲宽度的控制信号用于时钟延迟电路的延迟控制，从而实现每个数据接收系统（11）中的接收数据的最佳锁存定时。

29. 发明申请

US20050174145A1 Data transmission/reception system 失效
标题翻译：数据发送/接收系统
公开(公告)号：US20050174145A1
公开(公告)日：2005-08-11
申请号：US10513965
申请日：2003-08-27
申请人： Shiro Dosho , Yusuke Tokunaga , Yasuyuki Doi , Hirofumi Nakagawa , Yoshito Date , Tetsuro Ohmori , Kaori Nishikawa
发明人： Shiro Dosho , Yusuke Tokunaga , Yasuyuki Doi , Hirofumi Nakagawa , Yoshito Date , Tetsuro Ohmori , Kaori Nishikawa
IPC分类号： G09G3/36 , H04L25/02 , H04L25/49 , H03K19/094
CPC分类号： G09G3/3685 , G09G2310/027 , G09G2330/06 , H04L25/0272 , H04L25/4902
摘要： In the process of transferring a clock signal and a plurality of data signals which are in synchronization with the clock signal, a driving pulse width of a driver switch is feedback-controlled by a clock transmission system (12), whereby the clock signal is transmitted at a small amplitude. A control signal having the pulse width is used for controlling the driver switch in each data transmission system (13), whereby transfer of each data signal at a small amplitude is realized at the same time. Further, in a clock reception system (10), the control signal having the pulse width is used in delay control of a clock delay circuit, whereby an optimum latch timing of received data in each data reception system (11) is realized.
摘要翻译：在传送与时钟信号同步的时钟信号和多个数据信号的过程中，驱动器开关的驱动脉冲宽度被时钟传输系统（12）反馈控制，从而传输时钟信号在一个小幅度。具有脉冲宽度的控制信号用于控制每个数据传输系统（13）中的驱动器开关，从而同时实现以小幅度传送每个数据信号。此外，在时钟接收系统（10）中，具有脉冲宽度的控制信号用于时钟延迟电路的延迟控制，从而实现每个数据接收系统（11）中的接收数据的最佳锁存定时。

30. 发明授权

US07876166B2 Coupled ring oscillator and method for laying out the same 有权
标题翻译：耦合环形振荡器及其布置方法
公开(公告)号：US07876166B2
公开(公告)日：2011-01-25
申请号：US12831715
申请日：2010-07-07
申请人： Shiro Dosho , Shiro Sakiyama , Noriaki Takeda
发明人： Shiro Dosho , Shiro Sakiyama , Noriaki Takeda
IPC分类号： H03K3/03
CPC分类号： H03K3/0315
摘要： A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.
摘要翻译：耦合环形振荡器包括n个环形振荡器（20），每个环形振荡器（20）包括m个逆变器电路（10）和相位耦合回路（40），其中m×n个相位耦合电路（30）点在某一相位模式下，相互连接形成一个回路。逆变器电路（10）彼此连接的连接点和相位耦合电路（30）彼此连接的连接点彼此连接; 并且每个逆变器电路（10）连接在将相耦合电路（30）以一定比例分成两部分的两个点之间。

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