专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20070058440A1 Hole annealing methods of non-volatile memory cells 有权
标题翻译：非挥发性记忆体的空穴退火方法
公开(公告)号：US20070058440A1
公开(公告)日：2007-03-15
申请号：US11224597
申请日：2005-09-12
申请人： Wenpin Lu , Shaw Ku
发明人： Wenpin Lu , Shaw Ku
IPC分类号： G11C11/34
CPC分类号： G11C16/344 , G11C16/0466
摘要： Hole annealing methods are described after erasure of nitride storage memory cells for compensating trapped holes to minimize the holes from detrapping in order to reduce the amount of threshold voltage from drifting significantly higher. A soft hot electron program is used to selected nitride storage memory cells that have been detected to have a threshold voltage that is higher than a presetting threshold voltage (EV) minus a wordline delta X. The effect of the soft electron program neutralizes the excess holes introduced by erasure of nitride storage memory cells that decreases the amount of threshold voltage from drifting higher. In one embodiment, a hole annealing method describes a soft hot electron programming to nitride storage memory cells in a block of nitride memory array that have been determined to have a threshold voltage higher than the presetting threshold voltage minus the wordline delta X.
摘要翻译：在擦除用于补偿被捕获的孔的氮化物存储存储单元以最小化去除孔的孔之后描述空穴退火方法，以便将漂移的阈值电压的量显着地降低。软热电子程序被用于已被检测到具有高于预设阈值电压（EV）的阈值电压减去字线delta X的选定的氮化物存储单元。软电子程序的影响中和多余的空穴通过擦除氮化物存储存储器单元而引起的，其使得阈值电压的量从较高漂移减少。在一个实施例中，空穴退火方法描述了已经被确定具有高于预设阈值电压减去字线delta X的阈值电压的氮化物存储器阵列中的氮化物存储存储器单元的软热电子编程。

22. 发明授权

US6130452A Virtual ground flash cell with asymmetrically placed source and drain and method of fabrication 有权
标题翻译：具有不对称放置的源极和漏极的虚拟闪存单元和制造方法
公开(公告)号：US6130452A
公开(公告)日：2000-10-10
申请号：US134747
申请日：1998-08-14
申请人： Wenpin Lu , Mam-Tsung Wang
发明人： Wenpin Lu , Mam-Tsung Wang
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7883
摘要： A memory cell having asymmetrically placed source and drain diffusions which allows programming and erasure to be obtained across one of the source or drain diffusions which extends furthest beneath the floating gate while minimizing electron tunneling at the other of the source or drain diffusions which extends only minimally beneath the floating gate. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single virtual ground bit-line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a dielectric covering a semiconductor substrate of a first conductivity type; (2) forming a first and second column of floating gate cores on the dielectric; (3) implanting a first dopant adjacent the second column and displaced from the first column, the first dopant having a second conductivity type opposite the first conductivity type; (4) forming floating gate sidewalls in contact with the floating gate cores; (5) implanting a second dopant between the floating gate sidewalls, the second dopant having the second conductivity type; (6) forming a thermal oxide between the first and second column of floating gate cores such that oxide encroachments are formed below the floating gate cores of the first and second column and the first dopant is separated from the second column of floating gate cores by the first dielectric and the second dopant is separated from first column of the floating gate cores by the oxide encroachment; and (7) completing formation of control gate dielectric and control gates. The presence of tunneling and non-tunneling connections on the source and drain side of each cell improves the isolation between adjacent memory cells and minimizes the disturb problem.
摘要翻译：具有不对称放置的源极和漏极扩散的存储单元，其允许在源极或漏极扩散之间获得编程和擦除，该扩散最远在浮置栅极下方延伸，同时最小化源极或漏极扩散的另一个处的电子隧穿，在浮动门下面。一种非易失性半导体存储器件，包括单元的行和列布置，其中相邻列的单元共享单个虚拟接地位线。一种制造具有不对称源区和漏区的存储单元的方法，包括以下步骤：（1）形成覆盖第一导电类型的半导体衬底的电介质; （2）在电介质上形成第一和第二列浮栅; （3）在第二列附近注入第一掺杂物并从第一列移位，第一掺杂剂具有与第一导电类型相反的第二导电类型; （4）形成与浮动栅芯接触的浮动栅极侧壁; （5）在所述浮置栅极侧壁之间注入第二掺杂剂，所述第二掺杂物具有所述第二导电类型; （6）在第一和第二列的浮栅之间形成热氧化物，使得在第一和第二列的浮置栅芯之下形成氧化物侵蚀，并且第一掺杂剂通过第一电介质和第二掺杂剂通过氧化物侵蚀与浮栅的第一列分离; 和（7）完成控制栅介质和控制栅的形成。在每个单元的源极和漏极侧存在隧道和非隧道连接改善了相邻存储单元之间的隔离，并使干扰问题最小化。

23. 发明授权

US6055190A Device and method for suppressing bit line column leakage during erase verification of a memory cell 有权
标题翻译：用于在存储器单元的擦除验证期间抑制位线列泄漏的装置和方法
公开(公告)号：US6055190A
公开(公告)日：2000-04-25
申请号：US268557
申请日：1999-03-15
申请人： Wenpin Lu , Ying-Che Lo , Ming-Jye Chiou , Mam-Tsung Wang
发明人： Wenpin Lu , Ying-Che Lo , Ming-Jye Chiou , Mam-Tsung Wang
IPC分类号： G11C16/34 , G11C16/06
CPC分类号： G11C16/3445 , G11C16/344
摘要： A device and method of operation for an improved erase-verify device in which the non-selected cells, within a bit line column of an array of cells, remain inactive. Only the active cell is verified with minimum bit line column leakage associated with the operation of erase verification. Erase verification for a memory array is achieved by applying a source voltage (generally positive) to the common source line associated with a column of cells in the array. This will raise the threshold voltages of the cells (through the body effect of the semiconductor device) to a level higher than the predetermined minimum erased threshold voltage. The non-selected wordlines are coupled to a reference level below the threshold level of the cell (e.g. ground), and the selected wordline is coupled to a positive voltage which is a function of the source voltage. The source voltage is also added to the drain source voltage. The source voltage thereby serves as a feedback input to both the wordline and bit line inputs. Thereafter, a fixed drain-to-source bias is applied to the selected bit line column to conduct current for verification of the cell. The source voltage feedback allows the wordline voltage to be adjusted so that read current through the selected cell can be maintained at a desired level. Using this approach, the bit line column leakage caused by over-erased cells can be effectively suppressed, and an accurate verification result can be achieved.
摘要翻译：一种用于改进的擦除验证装置的装置和操作方法，其中在单元阵列的位线列内的未选择的单元保持不活动。只有活动单元格被验证与擦除验证的操作相关联的最小位线列泄漏。对存储器阵列的擦除验证是通过将源电压（通常为正）施加到与阵列中的一列单元相关联的公共源极线来实现的。这将使电池的阈值电压（通过半导体器件的本体效应）升高到高于预定的最小擦除阈值电压的电平。未选择的字线被耦合到低于单元的阈值电平（例如接地）的参考电平，并且所选择的字线耦合到作为源电压的函数的正电压。源极电压也被加到漏源电压上。因此，源电压用作对字线和位线输入的反馈输入。此后，将固定的漏极 - 源极偏压施加到所选择的位线列，以传导电流以验证电池。源电压反馈允许调节字线电压，使得通过所选择的单元的读取电流可以保持在期望的水平。利用这种方法，可以有效地抑制由过度擦除的单元引起的位线列泄漏，并且可以实现准确的验证结果。

24. 发明授权

US5963808A Method of forming an asymmetric bird's beak cell for a flash EEPROM 失效
标题翻译：形成快闪EEPROM的不对称鸟嘴单元的方法
公开(公告)号：US5963808A
公开(公告)日：1999-10-05
申请号：US783995
申请日：1997-01-15
申请人： Wenpin Lu , Tao-Cheng Lu , Mam-Tsung Wang
发明人： Wenpin Lu , Tao-Cheng Lu , Mam-Tsung Wang
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7883
摘要： A memory cell having an asymmetric source and drain connection to buried bit-lines providing a Fowler-Nordheim tunneling region and a non-tunneling region defined by a bird's beak encroachment on each of the cells. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single bit-line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a dielectric covering a semiconductor substrate of a first conductivity type; (2) forming a column of floating gates on the dielectric; (3) forming an inhibit mask adjacent a first side of the column of floating gates; (4) implanting a dopant adjacent the first side and a second side of the column of floating gates, the first dopant having a second conductivity type opposite the first conductivity type; (5) forming a thermal oxide adjacent the first and second side of the column of floating gates such that the dopant adjacent the first side of the column is separated from the floating gates by the dielectric and the dopant adjacent the second side of the column is separated from the floating gates by a bird's beak encroachment of the thermal oxide formation; and (6) completing formation of control gate dielectric and control gates.
摘要翻译：具有不对称的源极和漏极连接到具有Fowler-Nordheim隧道区域的掩埋位线的存储单元以及由每个单元上的鸟喙侵入限定的非隧穿区域。一种非易失性半导体存储器件，包括单元的行和列排列，其中相邻列的单元共享单个位线。一种制造具有不对称源区和漏区的存储单元的方法，包括以下步骤：（1）形成覆盖第一导电类型的半导体衬底的电介质; （2）在电介质上形成一列浮栅; （3）在所述浮栅的所述列的第一侧附近形成抑制掩模; （4）在所述浮栅的所述第一侧和所述第二侧附近注入掺杂剂，所述第一掺杂剂具有与所述第一导电类型相反的第二导电类型; （5）在浮置栅极列的第一和第二侧附近形成热氧化物，使得邻近该列的第一侧的掺杂剂通过电介质离开浮动栅极并且邻近该第二侧的掺杂剂是通过鸟喙侵蚀热氧化物形成与浮动门分离; （6）完成控制栅介质和控制栅的形成。

25. 发明授权

US5837584A Virtual ground flash cell with asymmetrically placed source and drain and method of fabrication 失效
标题翻译：具有不对称放置的源极和漏极的虚拟闪存单元和制造方法
公开(公告)号：US5837584A
公开(公告)日：1998-11-17
申请号：US783994
申请日：1997-01-15
申请人： Wenpin Lu , Mam-Tsung Wang
发明人： Wenpin Lu , Mam-Tsung Wang
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7883
摘要： A memory cell having asymmetrically placed source and drain diffusions which allows programming and erasure to be obtained across one of the source or drain diffusions which extends furthest beneath the floating gate while minimizing electron tunneling at the other of the source or drain diffusions which extends only minimally beneath the floating gate. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single virtual ground bit-line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of (1) forming a dielectric covering a semiconductor substrate of a first conductivity type; (2) forming a first and second column of floating gate cores on the dielectric; (3) implanting a first dopant adjacent the second column and displaced from the first column, the first dopant having a second conductivity type opposite the first conductivity type; (4) forming floating gate sidewalls in contact with the floating gate cores; (5) implanting a second dopant between the floating gate sidewalls, the second dopant having the second conductivity type; (6) forming a thermal oxide between the first and second column of floating gate cores such that oxide encroachments are formed below the floating gate cores of the first and second column and the first dopant is separated from the second column of floating gate cores by the first dielectric and the second dopant is separated from first column of the floating gate cores by the oxide encroachment; and (7) completing formation of control gate dielectric and control gates. The presence of tunneling and non-tunneling connections on the source and drain side of each cell improves the isolation between adjacent memory cells and minimizes the disturb problem.
摘要翻译：具有不对称放置的源极和漏极扩散的存储单元，其允许在源极或漏极扩散之间获得编程和擦除，该扩散最远在浮置栅极下方延伸，同时最小化源极或漏极扩散的另一个处的电子隧穿，在浮动门下面。一种非易失性半导体存储器件，包括单元的行和列布置，其中相邻列的单元共享单个虚拟接地位线。一种用于制造具有不对称源区和漏区的存储单元的方法，包括以下步骤：（1）形成覆盖第一导电类型的半导体衬底的电介质; （2）在电介质上形成第一和第二列浮栅; （3）在第二列附近注入第一掺杂物并从第一列移位，第一掺杂剂具有与第一导电类型相反的第二导电类型; （4）形成与浮动栅芯接触的浮动栅极侧壁; （5）在所述浮置栅极侧壁之间注入第二掺杂剂，所述第二掺杂物具有所述第二导电类型; （6）在第一和第二列的浮栅之间形成热氧化物，使得在第一和第二列的浮置栅芯之下形成氧化物侵蚀，并且第一掺杂剂通过第一电介质和第二掺杂剂通过氧化物侵蚀与浮栅的第一列分离; 和（7）完成控制栅介质和控制栅的形成。在每个单元的源极和漏极侧存在隧道和非隧道连接改善了相邻存储单元之间的隔离，并使干扰问题最小化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式