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21. 发明申请

US20060220215A1 Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same 有权
公开(公告)号：US20060220215A1
公开(公告)日：2006-10-05
申请号：US11378899
申请日：2006-03-17
申请人： Jong-Joo Lee
发明人： Jong-Joo Lee
IPC分类号： H01L23/52
CPC分类号： H01L23/5286 , H01L21/84 , H01L27/10894 , H01L27/1203 , H01L2224/05548 , H01L2224/05567 , H01L2224/05571 , H01L2924/00014 , H01L2924/0002 , H01L2224/05552
摘要： Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.

22. 发明申请

US20050260868A1 Test apparatus having intermediate connection board for package 有权
标题翻译：具有用于封装的中间连接板的测试装置
公开(公告)号：US20050260868A1
公开(公告)日：2005-11-24
申请号：US11001182
申请日：2004-12-02
申请人： Jong-Joo Lee
发明人： Jong-Joo Lee
IPC分类号： H01L21/66 , H01R12/00 , H01R13/24
CPC分类号： H01R13/2485 , G01R1/0466 , G01R1/0491 , H01R2201/20
摘要： A test apparatus may include a test socket having socket pins with a standard configuration. An intermediate connection board may be interposed between the test socket and a package that has solder balls with a non-standard configuration. The intermediate connection board may have contact balls and contact pads. The contact balls may be arranged in a configuration that is compatible with the standard socket pin configuration, and the contact pads may be arranged in a configuration that is compatible with the non-standard solder ball configuration.
摘要翻译：测试装置可以包括具有标准配置的插座引脚的测试插座。中间连接板可以插入在测试插座和具有非标准配置的焊球的封装之间。中间连接板可以具有接触球和接触垫。接触球可以布置成与标准插座销配置兼容的配置，并且接触焊盘可以布置成与非标准焊球配置兼容的配置。

23. 发明申请

US20130161830A1 SEMICONDUCTOR CHIPS HAVING REDISTRIBUTED POWER/GROUND LINES DIRECTLY CONNECTED TO POWER/GROUND LINES OF INTERNAL CIRCUITS AND METHODS OF FABRICATING THE SAME 有权
公开(公告)号：US20130161830A1
公开(公告)日：2013-06-27
申请号：US13775580
申请日：2013-02-25
申请人： Jong-Joo Lee
发明人： Jong-Joo Lee
IPC分类号： H01L23/522
CPC分类号： H01L23/5286 , H01L21/84 , H01L27/10894 , H01L27/1203 , H01L2224/05548 , H01L2224/05567 , H01L2224/05571 , H01L2924/00014 , H01L2924/0002 , H01L2224/05552
摘要： Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.

24. 发明申请

US20120314992A1 ELECTRONIC DEVICE HAVING OPTICAL COMMUNICATING PART 有权
标题翻译：具有光通信部分的电子设备
公开(公告)号：US20120314992A1
公开(公告)日：2012-12-13
申请号：US13441585
申请日：2012-04-06
申请人： Jong-Joo Lee
发明人： Jong-Joo Lee
IPC分类号： G02B6/12
CPC分类号： G02B6/428 , G02B6/4202 , G02B6/4257 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00
摘要： An electronic device includes a substrate having a first surface and a second surface, a semiconductor device disposed on a first region on the first surface of the substrate, a via structure penetrating the substrate, and including a conductor, an optical channel disposed in the via structure, and an optical-electrical converting device disposed at an end of the via structure, electrically connected to the semiconductor device through the conductor of the via structure, and optically connected to the optical channel.
摘要翻译：电子设备包括具有第一表面和第二表面的基板，设置在基板的第一表面上的第一区域上的半导体器件，穿透基板的通孔结构，并且包括导体，设置在通孔中的光通道结构，以及设置在通孔结构的端部处的光电转换装置，通过通孔结构的导体与半导体器件电连接，并且光学连接到光通道。

25. 发明授权

US08115315B2 Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same 有权
标题翻译：具有直接连接到内部电路的电源/接地线的重新分配的电源/接地线的半导体芯片及其制造方法
公开(公告)号：US08115315B2
公开(公告)日：2012-02-14
申请号：US12431956
申请日：2009-04-29
申请人： Jong-Joo Lee
发明人： Jong-Joo Lee
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L21/84 , H01L27/10894 , H01L27/1203 , H01L2224/05548 , H01L2224/05567 , H01L2224/05571 , H01L2924/00014 , H01L2924/0002 , H01L2224/05552
摘要： Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.
摘要翻译：提供了具有直接连接到内部电路的电源/接地线的重分布金属互连的半导体芯片的实施例。半导体芯片的实施例包括形成在半导体衬底上的内部电路。芯片焊盘设置在半导体衬底上。芯片焊盘通过内部互连电连接到内部电路。钝化层设置在芯片焊盘的上方。在钝化层上设置重新分布的金属互连。再分布的金属互连通过穿孔至少钝化层的通孔和芯片焊盘开口将内部互连直接连接到芯片焊盘。还提供了制造半导体芯片的方法。

26. 发明授权

US07745922B2 Package board having internal terminal interconnection and semiconductor package employing the same 有权
标题翻译：具有内部端子互连的封装板和采用其的半导体封装
公开(公告)号：US07745922B2
公开(公告)日：2010-06-29
申请号：US11424605
申请日：2006-06-16
申请人： Jong-Joo Lee
发明人： Jong-Joo Lee
IPC分类号： H01L23/52
CPC分类号： H01L23/50 , H01L23/49822 , H01L23/66 , H01L2224/05001 , H01L2224/05022 , H01L2224/05024 , H01L2224/05548 , H01L2224/16225 , H01L2924/00014 , H01L2924/3011 , H01L2224/05599 , H01L2224/05099
摘要： A package board is provided. The package board includes a board body having a front surface and a back surface. A first power pad, a first ground pad, a first signal pad, a first internal terminal pad and a second internal terminal pad are disposed on the front surface of the board body, and a second power pad, a second ground pad and a second signal pad are disposed on the back surface of the board body. The second power pad, the second ground pad and the second signal pad are electrically connected to the first power pad, the first ground pad and the first signal pad, respectively. An internal terminal interconnection is provided in a bulk region of the board body or on a surface of the board body. The internal terminal interconnection electrically connects the first internal terminal pad to the second internal terminal pad. A semiconductor package employing the package board is also provided.
摘要翻译：提供一个包装板。封装板包括具有前表面和后表面的板体。第一电源焊盘，第一接地焊盘，第一信号焊盘，第一内部端子焊盘和第二内部端子焊盘设置在板主体的前表面上，第二电源焊盘，第二接地焊盘和第二焊盘信号垫设置在板体的背面。第二电源焊盘，第二接地焊盘和第二信号焊盘分别电连接到第一电源焊盘，第一接地焊盘和第一信号焊盘。内部端子互连设置在电路板主体的主体区域或电路板主体的表面上。内部端子互连将第一内部端子焊盘电连接到第二内部端子焊盘。还提供了采用封装板的半导体封装。

27. 发明申请

US20100117215A1 PLANAR MULTI SEMICONDUCTOR CHIP PACKAGE 有权
标题翻译：平面多芯半导体芯片封装
公开(公告)号：US20100117215A1
公开(公告)日：2010-05-13
申请号：US12689717
申请日：2010-01-19
申请人： Jong-Joo Lee
发明人： Jong-Joo Lee
IPC分类号： H01L23/52 , H01L23/538
CPC分类号： H01L25/18 , H01L23/481 , H01L24/02 , H01L24/12 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L2224/0401 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2224/16145 , H01L2224/16225 , H01L2224/48227 , H01L2224/73207 , H01L2224/73253 , H01L2224/73257 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06568 , H01L2225/06589 , H01L2225/06596 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Provided are a planar multi semiconductor chip package in which a processor and a memory device are connected to each other via a through electrode and a method of manufacturing the planar multi semiconductor chip package. The planar multi semiconductor chip package includes: a substrate comprising a plurality of first circuit patterns on a first surface and a plurality of second circuit patterns on a second surface; a first semiconductor chip comprising a plurality of memory devices arranged on the substrate, wherein first memory devices surround at least a portion of second memory devices; a second semiconductor chip stacked on the first semiconductor chip and corresponding to the second memory devices; and a plurality of through electrodes arranged on the second memory devices and connecting the first and second semiconductor chips to the second circuit pattern of the substrate.
摘要翻译：提供一种平面多半导体芯片封装，其中处理器和存储器件经由通孔彼此连接，以及制造平面多芯片封装的方法。平面多晶半导体芯片封装包括：在第一表面上包括多个第一电路图案的基板和在第二表面上的多个第二电路图案; 包括布置在所述基板上的多个存储器件的第一半导体芯片，其中第一存储器件围绕第二存储器件的至少一部分; 堆叠在第一半导体芯片上并对应于第二存储器件的第二半导体芯片; 以及布置在第二存储器件上并将第一和第二半导体芯片连接到基板的第二电路图案的多个贯通电极。

28. 发明申请

US20100044847A1 SEMICONDUCTOR CHIP INCLUDING A CHIP VIA PLUG PENETRATING A SUBSTRATE, A SEMICONDUCTOR STACK, A SEMICONDUCTOR DEVICE PACKAGE AND AN ELECTRONIC APPARATUS INCLUDING THE SEMICONDUCTOR CHIP 有权
标题翻译：半导体芯片，其包括通过插入底片的薄片，半导体堆叠，半导体器件封装和包括半导体芯片的电子设备
公开(公告)号：US20100044847A1
公开(公告)日：2010-02-25
申请号：US12545323
申请日：2009-08-21
申请人： Jong-Joo Lee
发明人： Jong-Joo Lee
IPC分类号： H01L25/11 , H01L23/48 , H01L23/52
CPC分类号： H01L23/525 , H01L23/481 , H01L23/49816 , H01L24/06 , H01L24/12 , H01L24/16 , H01L24/48 , H01L24/83 , H01L25/0657 , H01L2224/02372 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/06136 , H01L2224/13009 , H01L2224/13024 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/2518 , H01L2224/2929 , H01L2224/293 , H01L2224/4824 , H01L2224/83851 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00011 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/19041 , H01L2924/3011 , H01L2924/3025 , H01L2224/29075 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor chip including a chip via plug penetrating a substrate, a semiconductor stack thereof, a semiconductor device package thereof, and an electronic apparatus having the same are disclosed. The semiconductor chip comprising, a substrate including an inner semiconductor circuit, a conductive redistribution structure formed on the substrate including a conductive redistribution interconnection and a conductive redistribution via plug, wherein the redistribution via plug is connected to the inner semiconductor circuit; a conductive chip pad formed on the substrate, and a conductive chip via plug configured to penetrate the substrate and electrically connected to the redistribution structure.
摘要翻译：公开了一种半导体芯片，其包括穿过基板的芯片通孔插塞，其半导体叠层，其半导体器件封装以及具有该半导体芯片的电子设备。所述半导体芯片包括：包括内部半导体电路的基板，形成在所述基板上的导电再分布结构，所述导电再分布结构包括导电再分配互连和通过插头的导电再分布，其中所述再分配经由插头连接到所述内部半导体电路; 形成在所述基板上的导电芯片焊盘，以及被配置为穿透所述基板并电连接到所述再分布结构的导电芯片通孔插头。

29. 发明申请

US20050199993A1 Semiconductor package having heat spreader and package stack using the same 有权
标题翻译：具有散热器和使用其的封装堆叠的半导体封装
公开(公告)号：US20050199993A1
公开(公告)日：2005-09-15
申请号：US11065822
申请日：2005-02-24
申请人： Jong-Joo Lee , Young-Hee Song
发明人： Jong-Joo Lee , Young-Hee Song
IPC分类号： H01L23/36 , H01L23/02
CPC分类号： H01L23/3157 , H01L23/13 , H01L23/552 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/05026 , H01L2224/05573 , H01L2224/16225 , H01L2224/291 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/4824 , H01L2224/73204 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2225/1094 , H01L2924/00014 , H01L2924/01079 , H01L2924/07802 , H01L2924/15151 , H01L2924/15331 , H01L2924/3025 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A semiconductor package which can be stacked to form a package stack that includes a semiconductor chip with bonding pads, a board having contact pads on its upper surface and bump pads on its lower surface, a heat spreader attached to the rear side of the semiconductor chip and covering the upper surface of the board, and external contact terminals including ground terminals and signal terminals formed on the bump pads. The contact pads of the board include ground contact pads connected with the ground terminals and signal contact pads connected with the signal terminals. The heat spreader includes indented parts to expose the signal contact pads and protruded parts to cover the ground contact pads which are exposed through holes formed on the protruded parts on the peripheral part of the heat spreader. The semiconductor package can alternatively have the heat spreader attached to the lower surface of the board.
摘要翻译：一种半导体封装，其可堆叠形成包括具有接合焊盘的半导体芯片的封装堆叠，在其上表面上具有接触焊盘的板和其下表面上的凸块焊盘;附接到半导体芯片的后侧的散热器并覆盖电路板的上表面，以及包括接地端子和形成在凸块上的信号端子的外部接触端子。板的接触垫包括与接地端子连接的接地焊盘和与信号端子连接的信号接触焊盘。散热器包括凹陷部分，以暴露信号接触焊盘和突出部分，以覆盖通过形成在散热器的周边部分上的突出部分上的孔暴露的接地焊盘。半导体封装也可以具有附着到板的下表面的散热器。

30. 发明申请

US20050104184A1 Semiconductor chip package and method 审中-公开
标题翻译：半导体芯片封装及方法
公开(公告)号：US20050104184A1
公开(公告)日：2005-05-19
申请号：US10983576
申请日：2004-11-09
申请人： Mee-Hyun Ahn , Jong-Joo Lee
发明人： Mee-Hyun Ahn , Jong-Joo Lee
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L21/607 , H01L21/82 , H01L21/822 , H01L23/48 , H01L23/50 , H01L23/538 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/04 , H01L23/02
CPC分类号： H01L24/85 , H01L23/50 , H01L24/06 , H01L24/48 , H01L25/0657 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L2225/0651 , H01L2225/06527 , H01L2225/06582 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/10161 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2224/78 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A unit semiconductor chip package may includes a semiconductor chip, a first series of bonding pads in a first area, a second series of bonding pads in a second area, a plurality of bonding fingers provided on a substrate and a plurality of bonding wires. Each of the first series of bonding pads may be electrically connected to a corresponding one of the plurality of bonding fingers by one bonding wire and each of the second series of bonding pad may be electrically connected to one of the plurality of bonding fingers by at least two bonding wires or the plurality of bonding wires electrically connecting the first series of bonding pads may be longer and the plurality of bonding wires electrically connecting the second series of bonding pads may be longer or shorter.
摘要翻译：单元半导体芯片封装可以包括半导体芯片，第一区域中的第一系列接合焊盘，第二区域中的第二系列焊盘，设置在基板上的多个接合指状物和多个接合线。第一系列接合焊盘中的每一个可以通过一个接合线电连接到多个接合指的相应一个，并且第二系列接合焊盘中的每一个可以至少电连接到多个接合指中的一个电连接第一系列接合焊盘的两个接合线或多个接合线可以更长，并且电连接第二接合焊盘的多个接合线可以更长或更短。

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