会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 22. 发明申请
    • PIN DIODE
    • PIN二极管
    • US20120299164A1
    • 2012-11-29
    • US13520361
    • 2010-02-16
    • Yoshikazu NishimuraHirofumi YamamotoTakeyoshi Uchino
    • Yoshikazu NishimuraHirofumi YamamotoTakeyoshi Uchino
    • H01L29/868
    • H01L29/8611H01L29/0619H01L29/0638
    • A PIN diode having improved avalanche resistance is provided. The PIN diode includes: a semiconductor substrate 11 that includes an N+ semiconductor layer 1, and an N− semiconductor layer 2; a P-type anode region 15 that is formed by selective impurity diffusion into an outer surface of the N− semiconductor layer 2; and an anode electrode 17 that is conducted to the anode region 15 through a contact region 17c in the anode region 15. The anode region 15 has a substantially rectangular outer edge of which four sides are adapted to be linear parts B2 and four vertices are adapted to be curved parts B1, and outside the contact region 17c, N-type non-diffusion corner regions 16 that extend along the curved parts B1 are respectively formed.
    • 提供了具有改善的雪崩阻力的PIN二极管。 PIN二极管包括:包括N +半导体层1和N半导体层2的半导体衬底11; 通过选择性杂质扩散到N半导体层2的外表面中形成的P型阳极区域15; 以及通过阳极区域15中的接触区域17c而导引到阳极区域15的阳极电极17.阳极区域15具有基本上矩形的外边缘,其四条边适于线性部分B2,并且四个顶点被适配 作为弯曲部分B1,并且在接触区域17c的外部,分别形成沿着弯曲部分B1延伸的N型非扩散角区域16。
    • 26. 发明授权
    • Active bias circuit having Wilson and Widlar configurations
    • 有源偏置电路具有Wilson和Widlar配置
    • US06639452B2
    • 2003-10-28
    • US10319995
    • 2002-12-16
    • Fuminobu OnoYoshikazu Nishimura
    • Fuminobu OnoYoshikazu Nishimura
    • G05F110
    • G05F3/262G05F3/205
    • An active bias circuit having a combined configuration of the Wilson and Widlar current source configurations is provided, which makes it possible to set the output bias voltage at approximately zero (0V) even if a reference voltage applied to generate a reference current does not reach 0V. This circuit comprises cascode-connected first and second transistors, cascode-connected third and fourth transistors, and a resistor with a specific voltage drop generated by a current flowing through the same. The absolute value of the output bias voltage is decreased by the value of the voltage drop of the resistor compared with the case where the resistor is not provided. The resistor is provided between the gates/bases of the first and third transistors, or between the gate/base and source/emitter of the fourth transistor.
    • 提供了具有Wilson和Widlar电流源配置的组合配置的主动偏置电路,这使得即使施加用于产生参考电流的参考电压没有达到0V,也可以将输出偏置电压设置在大约零(0V) 。 该电路包括共源共栅连接的第一和第二晶体管,共源共栅连接的第三和第四晶体管,以及具有由流过该晶体管的电流产生的特定电压降的电阻器。 与未设置电阻器的情况相比,输出偏置电压的绝对值减小电阻器的电压降值。 电阻器设置在第一和第三晶体管的栅极/基极之间,或第四晶体管的栅极/基极和源极/发射极之间。
    • 28. 发明授权
    • AM synchronous detecting circuit
    • AM同步检测电路
    • US4633187A
    • 1986-12-30
    • US727561
    • 1985-04-26
    • Yoshikazu NishimuraYoshimi YasukouchiHisao Asakura
    • Yoshikazu NishimuraYoshimi YasukouchiHisao Asakura
    • H04N9/45H04N9/66H03D3/06
    • H04N9/66
    • A demodulating circuit for an amplitude-modulated signal comprises an input terminal to be supplied with an input signal comprising at least a modulated carrier signal amplitude-modulated by an information signal, the modulated carrier signal having a predetermined phase; an oscillator for generating a first demodulating carrier the phase of which is displaced from that of the modulated carrier signal by 90.degree., and a second demodulating carrier which has the same phase as that of the modulated carrier signal; a first synchronous demodulator for demodulating the input signal with the first demodulating carrier; a second synchronous demodulator for demodulating the input signal with the second demodulating carrier; a level detector for detecting the level of a predetermined portion of the demodulated output of the first synchronous detector; a control circuit supplied with the output of the level detector for controlling the oscillator so that the phase of the second demodulating carrier is synchronous with that of the modulated carrier signal; and an output terminal connected to the second synchronous detector for receiving the demodulated information signal from the second synchronous detector. The demodulator circuitry according to the invention performs stable demodulation without using a limiter, and with the phase of the carrier signal for demodulation under its control, thus being free from dependence of the phase of carrier signals for demodulation on the level of input signals.
    • 用于幅度调制信号的解调电路包括:输入端,其被提供有至少包括由信息信号幅度调制的调制载波信号的输入信号,调制载波信号具有预定相位; 用于产生第一解调载波的振荡器,该第一解调载波的相位与调制载波信号的相位相差90°;以及第二解调载波,其具有与调制载波信号相同的相位; 第一同步解调器,用于利用第一解调载波解调输入信号; 第二同步解调器,用于用第二解调载波解调输入信号; 电平检测器,用于检测第一同步检测器的解调输出的预定部分的电平; 提供有电平检测器的输出的控制电路,用于控制振荡器,使得第二解调载波的相位与调制载波信号的相位同步; 以及连接到第二同步检测器的输出端子,用于从第二同步检测器接收解调信息信号。 根据本发明的解调器电路在不使用限制器的情况下执行稳定的解调,并且在其控制下用于解调的载波信号的相位,从而不依赖于用于解调的载波信号的相位对输入信号的电平。
    • 29. 发明授权
    • Pin diode
    • 引脚二极管
    • US08564105B2
    • 2013-10-22
    • US13520361
    • 2010-02-16
    • Yoshikazu NishimuraHirofumi YamamotoTakeyoshi Uchino
    • Yoshikazu NishimuraHirofumi YamamotoTakeyoshi Uchino
    • H01L31/075H01L31/105H01L31/117
    • H01L29/8611H01L29/0619H01L29/0638
    • A PIN diode having improved avalanche resistance is provided. The PIN diode includes: a semiconductor substrate 11 that includes an N+ semiconductor layer 1, and an N− semiconductor layer 2; a P-type anode region 15 that is formed by selective impurity diffusion into an outer surface of the N− semiconductor layer 2; and an anode electrode 17 that is conducted to the anode region 15 through a contact region 17c in the anode region 15. The anode region 15 has a substantially rectangular outer edge of which four sides are adapted to be linear parts B2 and four vertices are adapted to be curved parts B1, and outside the contact region 17c, N-type non-diffusion corner regions 16 that extend along the curved parts B1 are respectively formed.
    • 提供了具有改善的雪崩阻力的PIN二极管。 PIN二极管包括:包括N +半导体层1和N半导体层2的半导体衬底11; 通过选择性杂质扩散到N半导体层2的外表面中形成的P型阳极区域15; 以及通过阳极区域15中的接触区域17c而导引到阳极区域15的阳极电极17.阳极区域15具有基本上矩形的外边缘,其四条边适于线性部分B2,并且四个顶点被适配 作为弯曲部分B1,并且在接触区域17c的外部,分别形成沿着弯曲部分B1延伸的N型非扩散角区域16。