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21. 发明授权

US5790447A High-memory capacity DIMM with data and state memory 失效
标题翻译：具有数据和状态存储器的高内存容量DIMM
公开(公告)号：US5790447A
公开(公告)日：1998-08-04
申请号：US747975
申请日：1996-11-12
申请人： James P. Laudon , Daniel E. Lenoski , John Manton
发明人： James P. Laudon , Daniel E. Lenoski , John Manton
IPC分类号： G11C7/00 , G11C5/00 , G11C5/02 , G11C11/00 , G11C11/401 , G11C5/06
CPC分类号： G11C5/04 , G11C5/00
摘要： A high memory capacity dual in-line memory modules (DIMM) for use in a directory-based, distributed shared memory multiprocessor computer system includes a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM can be configured in a plurality of storage capacities.
摘要翻译：用于基于目录的分布式共享存储器多处理器计算机系统中的高存储容量双列直插存储器模块（DIMM）包括用于存储数据的数据存储器和用于存储对应于至少一部分的状态或目录信息的状态存储器的数据。 DIMM允许独立访问数据和状态信息。 DIMM可以配置成多个存储容量。

22. 发明授权

US5185870A System to determine if modification of first macroinstruction to execute in fewer clock cycles 失效
标题翻译：系统确定第一个宏指令的修改是否在较少的时钟周期内执行
公开(公告)号：US5185870A
公开(公告)日：1993-02-09
申请号：US926132
申请日：1992-08-05
申请人： Daniel E. Lenoski
发明人： Daniel E. Lenoski
IPC分类号： G06F9/318 , G06F9/38
CPC分类号： G06F9/30181 , G06F9/3836 , G06F9/3853 , G06F9/3867
摘要： A method and mechanism for shortening the execution time of certain macro-instructions by looking at both a present macro-instruction and a next macro-instruction. The invention includes two, interrelated aspects for accomplishing this. First, a first operation of a next macro-instruction is performed concurrently with a last operation of a current macro-instruction. Second, the next macro-instruction is decoded to determine the minimum number of clock cycles it requires. If this minimum number is below a specified number, the micro operations of the present instruction are modified to perform appropriate set-up operations for the next macro-instruction to enable it to be completed in the computed minimum number of clock cycles.
摘要翻译：一种通过查看当前宏指令和下一个宏指令来缩短某些宏指令的执行时间的方法和机制。本发明包括两个相互关联的方面来实现这一点。首先，与当前宏指令的最后一个操作同时执行下一个宏指令的第一操作。第二，下一个宏指令被解码以确定其所需的最小时钟周期数。如果该最小数量低于指定数量，则修改当前指令的微操作以对下一个宏指令执行适当的设置操作，以使其能够以所计算的最小时钟周期数完成。

23. 发明授权

US07500068B1 Method and system for managing memory in a multiprocessor system 有权
标题翻译：用于管理多处理器系统中的存储器的方法和系统
公开(公告)号：US07500068B1
公开(公告)日：2009-03-03
申请号：US11426538
申请日：2006-06-26
申请人： Daniel E. Lenoski , Jeffrey S. Kuskin , William A. Huffman , Michael S. Woodacre
发明人： Daniel E. Lenoski , Jeffrey S. Kuskin , William A. Huffman , Michael S. Woodacre
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F15/167
CPC分类号： G06F12/0817 , G06F12/0813
摘要： A method and system for managing memory in a multiprocessor system includes defining the plurality of processor coherence domains within a system coherence domain of the multiprocessor system. The processor coherence domains each include a plurality of processors and a processor memory. Shared access to data in the processor memory of each processor coherence domain is provided only to elements of the multiprocessor system within the processor coherence domain. Non-shared access to data in the processor memory of each processor coherence domain is provided to elements of the multiprocessor system within and outside of the processor coherence domain.
摘要翻译：用于管理多处理器系统中的存储器的方法和系统包括在多处理器系统的系统相干域内定义多个处理器相干域。处理器相干域各自包括多个处理器和处理器存储器。每个处理器一致性域的处理器存储器中的数据的共享访问仅提供给处理器相干域内的多处理器系统的元件。每个处理器相干域的处理器存储器中的数据的非共享访问被提供给处理器相干域内部和外部的多处理器系统的元件。

24. 发明授权

US06735173B1 Method and apparatus for accumulating and distributing data items within a packet switching system 有权
标题翻译：用于在分组交换系统内累积和分发数据项的方法和装置
公开(公告)号：US06735173B1
公开(公告)日：2004-05-11
申请号：US09520688
申请日：2000-03-07
申请人： Daniel E. Lenoski , Jonathan S. Turner
发明人： Daniel E. Lenoski , Jonathan S. Turner
IPC分类号： H04L1226
CPC分类号： H04L47/10 , H04L47/15 , H04L47/33 , H04L47/35
摘要： Methods and apparatus are disclosed for accumulating and distributing information in a packet switching system. For example, it is desirable in certain packet switching systems to communicate the status of internal queues and other port status information from an individual port to all other ports (or at least those which are communicating with the individual port). The amount of information being sent from the individual port is typically very small, such as on the order of a few bits or bytes. By accumulating the information and then broadcasting the collected flow control information, a vast amount of switch fabric resources (e.g., bandwidth) can be saved. In one implementation, flow control information is sent to a destination (e.g., a “mailbox”) within a packet switching fabric which includes a memory in which flow control information is accumulated. After a period of time or based on the occurrence of some event, the accumulated flow control information is distributed. This same mechanism may be used to distribute most any type of information (e.g., flow control information, signaling information, and data internal or external to a packet switch or packet switching system).
摘要翻译：公开了用于在分组交换系统中累积和分发信息的方法和装置。例如，在某些分组交换系统中，期望将内部队列的状态和其他端口状态信息从单个端口传送到所有其他端口（或至少是与各个端口通信的端口）。从单个端口发送的信息量通常非常小，例如几位或几位的数量级。通过累积信息，然后广播收集的流量控制信息，可以节省大量的交换结构资源（例如，带宽）。在一个实现中，将流量控制信息发送到分组交换结构内的目的地（例如，“邮箱”），该分组交换结构包括其中积累有流量控制信息的存储器。经过一段时间后或者基于某些事件的发生，分布了累积的流量控制信息。这种相同的机制可以用于分发大多数任何类型的信息（例如，流控制信息，信令信息，以及分组交换机或分组交换系统的内部或外部的数据）。

25. 发明授权

US06049476A High memory capacity DIMM with data and state memory 失效
标题翻译：具有数据和状态存储器的高内存容量DIMM
公开(公告)号：US06049476A
公开(公告)日：2000-04-11
申请号：US126944
申请日：1998-07-31
申请人： James P. Laudon , Daniel E. Lenoski , John Manton , Michael E. Anderson
发明人： James P. Laudon , Daniel E. Lenoski , John Manton , Michael E. Anderson
IPC分类号： G11C7/00 , G11C5/00 , G11C5/02 , G11C11/00 , G11C11/401
CPC分类号： G11C5/04 , G11C5/00
摘要： A high memory capacity dual in-line memory module (DIMM) for use in a directory-based, distributed shared memory multiprocessor computer system including a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM can be configured in a plurality of storage capacities.
摘要翻译：一种用于基于目录的分布式共享存储器多处理器计算机系统的高存储容量双列直插式存储器模块（DIMM），包括用于存储数据的数据存储器和用于存储对应于至少一部分的状态或目录信息的状态存储器的数据。 DIMM允许独立访问数据和状态信息。 DIMM可以配置成多个存储容量。

26. 发明授权

US5727150A Apparatus and method for page migration in a non-uniform memory access (NUMA) system 失效
标题翻译：在不均匀存储器访问（NUMA）系统中页面迁移的装置和方法
公开(公告)号：US5727150A
公开(公告)日：1998-03-10
申请号：US766363
申请日：1996-12-17
申请人： James P. Laudon , Daniel E. Lenoski
发明人： James P. Laudon , Daniel E. Lenoski
IPC分类号： G06F12/06 , G06F12/08 , G06F12/12 , G06F13/00
CPC分类号： G06F12/122 , G06F12/08
摘要： A page migration controller is described. The page migration controller determines whether a memory page addressed by a memory access request should be migrated from a local processing node to a requester processing node. The page migration controller accesses an array to obtain a first count associated with the addressed memory page and the requester processing node, and a second count associated with the addressed memory page and the local processing node. The first count is incremented, and then the second count is subtracted from the incremented first count to obtain a difference between the second count and the incremented first count. A comparator determines whether the difference is greater than a migration threshold value. If the difference is greater than the migration threshold value, then a migration interrupt is issued.
摘要翻译：描述页面迁移控制器。页面迁移控制器确定由存储器访问请求寻址的存储器页是否应当从本地处理节点迁移到请求者处理节点。页面迁移控制器访问阵列以获得与所寻址的存储器页面和请求者处理节点相关联的第一计数，以及与寻址的存储器页面和本地处理节点相关联的第二计数。第一计数增加，然后从增加的第一计数中减去第二计数，以获得第二计数和递增的第一计数之间的差。比较器确定差异是否大于迁移阈值。如果差值大于迁移阈值，则发出迁移中断。

27. 发明授权

US5032983A Entry point mapping and skipping method and apparatus 失效
标题翻译：入口点映射和跳过方法和设备
公开(公告)号：US5032983A
公开(公告)日：1991-07-16
申请号：US409978
申请日：1989-09-18
申请人： Peter L. Fu , Daniel E. Lenoski
发明人： Peter L. Fu , Daniel E. Lenoski
IPC分类号： G06F9/26
CPC分类号： G06F9/26 , G06F9/261
摘要： A fixed entry-point map to produce an entry point address of a first micro-instruction for a particular macro-instruction. That address is then incremented by a fixed number to produce the second, third, etc. micro-instructions for that macro-instruction. In a first embodiment, after a fixed number of these address skips, the addresses are incremented by 1 so that successive micro-instructions are in adjacent address locations. In a second embodiment, the number of skips is variable.
摘要翻译：固定入口点映射，用于产生用于特定宏指令的第一微指令的入口点地址。该地址然后递增固定数字，以产生该宏指令的第二，第三等微指令。在第一实施例中，在固定数目的这些地址跳过之后，将地址递增1，使得连续的微指令位于相邻地址位置。在第二实施例中，跳过次数是可变的。

28. 发明授权

US4899307A Stack with unary encoded stack pointer 失效
标题翻译：与一元编码的堆栈指针堆栈
公开(公告)号：US4899307A
公开(公告)日：1990-02-06
申请号：US36607
申请日：1987-04-10
申请人： Daniel E. Lenoski
发明人： Daniel E. Lenoski
IPC分类号： G11C7/00 , G06F7/78 , G06F9/34
CPC分类号： G06F7/785
摘要： A stack with a unary encoded stack pointer which uses the position of a single bit to point to the top of the stack. A number of multi-bit latches are used to store the data elements in the stack. A serial, bidirectional shift register is loaded with all digital zeros except for a position having a digital one (the pointer) which is coupled to the register containing the top of the stack. As new data elements are pushed onto or popped off of the top of the stack, the pointer is shifted right or left accordingly.

29. 发明授权

US4843608A Cross-coupled checking circuit 失效
标题翻译：交叉耦合检查电路
公开(公告)号：US4843608A
公开(公告)日：1989-06-27
申请号：US039565
申请日：1987-04-16
申请人： Peter L. Fu , Daniel E. Lenoski
发明人： Peter L. Fu , Daniel E. Lenoski
IPC分类号： G06F11/22 , G01R31/3185 , G06F11/08 , G06F11/10 , G06F11/16
CPC分类号： G06F11/1633 , G01R31/3185 , G06F11/08 , G06F11/10
摘要： A cross-coupled checking circuit is disclosed in which two identical integrated circuit chips are configured in a complementary manner and connected in parallel to the same inputs and outputs. One chip drives the data output data and the other chip drives the check symbol output corresponding to the output data. Each chip generates internal results and compares them to the output driven by the other chip.

30. 发明授权

US4825356A Microcoded microprocessor with shared ram 失效
标题翻译：具有共享RAM的微编码微处理器
公开(公告)号：US4825356A
公开(公告)日：1989-04-25
申请号：US31477
申请日：1987-03-27
申请人： Daniel E. Lenoski
发明人： Daniel E. Lenoski
IPC分类号： G06F9/22 , G06F9/26 , G06F9/28 , G06F9/30
CPC分类号： G06F9/264 , G06F9/226
摘要： A processor system utilizing a single shared RAM array, for storing microcode and other function data, with the shared array coupled to the processor by a single shared ADR/DATA bus. In one embodiment, an onboard ROM stores selected lines of microcode and a ROM accessing system supplies microcode from the ROM when the shared RAM array is busy performing some other RAM function.

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