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21. 发明授权

US08691693B2 Methods of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08691693B2
公开(公告)日：2014-04-08
申请号：US13290285
申请日：2011-11-07
申请人： Sang-Jin Kim , Jong-Chan Shin , Yong-Kug Bae , Do-Hyoung Kim , Dong-Woon Park
发明人： Sang-Jin Kim , Jong-Chan Shin , Yong-Kug Bae , Do-Hyoung Kim , Dong-Woon Park
IPC分类号： H01L21/44 , H01L29/40
CPC分类号： H01L21/76895 , H01L21/28518 , H01L21/31144 , H01L21/76897 , H01L21/823418 , H01L21/823475 , H01L21/823481 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： In a method of manufacturing a semiconductor device, a first etching mask and a second etching mask are formed sequentially on a metal gate structure on a substrate and a first insulating interlayer covering a sidewall of the metal gate structure respectively. An opening is formed to expose a top surface of the substrate by removing a portion of the first insulating interlayer not overlapped with the first etching mask or the second etching mask. A metal silicide pattern is formed on the exposed top surface of the substrate. A plug on the metal silicide pattern is formed to fill a remaining portion of the opening. Further, a planarization layer may be used as the second etching mask.
摘要翻译：在制造半导体器件的方法中，依次在基板上的金属栅极结构和覆盖金属栅极结构的侧壁的第一绝缘夹层上形成第一蚀刻掩模和第二蚀刻掩模。通过除去与第一蚀刻掩模或第二蚀刻掩模不重叠的第一绝缘夹层的一部分，形成开口以暴露基板的顶表面。在衬底的暴露的顶表面上形成金属硅化物图案。形成金属硅化物图案上的塞子以填充开口的剩余部分。此外，可以使用平坦化层作为第二蚀刻掩模。

22. 发明授权

US08598127B2 Peptides for inhibiting MDM2 function 有权
标题翻译：用于抑制MDM2功能的肽
公开(公告)号：US08598127B2
公开(公告)日：2013-12-03
申请号：US11547730
申请日：2004-12-29
申请人： Kyou-Hoon Han , Seung-Wook Chi , Hyun-Jeong Kim , Si-Hyung Lee , Min-Jung Ahn , Do-Hyoung Kim , Jae-Sung Kim , Shin-Ae Park
发明人： Kyou-Hoon Han , Seung-Wook Chi , Hyun-Jeong Kim , Si-Hyung Lee , Min-Jung Ahn , Do-Hyoung Kim , Jae-Sung Kim , Shin-Ae Park
IPC分类号： A61K38/06 , A61K38/00
CPC分类号： C07K14/4746
摘要： Disclosed are peptides for inhibiting mdm2 (mouse double minute 2) and a pharmaceutical composition comprising the same.
摘要翻译：公开了抑制mdm2（小鼠双倍分子2）的肽和包含其的药物组合物。

23. 发明授权

US08592265B2 Method for manufacturing semiconductor device having a metal gate electrode 有权
标题翻译：具有金属栅电极的半导体器件的制造方法
公开(公告)号：US08592265B2
公开(公告)日：2013-11-26
申请号：US13242382
申请日：2011-09-23
申请人： Dong-Kwon Kim , Young-Ju Park , Dong-Hyuk Yeam , Yoo-Jung Lee , Myeong-Cheol Kim , Do-Hyoung Kim , Heung-Sik Park
发明人： Dong-Kwon Kim , Young-Ju Park , Dong-Hyuk Yeam , Yoo-Jung Lee , Myeong-Cheol Kim , Do-Hyoung Kim , Heung-Sik Park
IPC分类号： H01L21/338
CPC分类号： H01L21/28132 , H01L21/28114 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/6656
摘要： Example embodiments relate to a method for manufacturing a semiconductor device, wherein a metal gate electrode therein may be formed without a void in a lower portion of the metal gate electrode. The method may include providing a substrate, forming a dummy gate electrode on the substrate, forming a gate spacer on the substrate to be contiguous to the dummy gate electrode, forming a first recess by simultaneously removing a portion of the dummy gate electrode and a portion of the gate spacer, the first recess having an upper end wider than a lower end, forming a second recess by removing the dummy gate electrode remaining after forming the first recess, and forming a metal gate electrode by depositing a metal to fill the first and second recesses.
摘要翻译：示例性实施例涉及用于制造半导体器件的方法，其中可以在金属栅电极的下部中形成其中的金属栅极电极，而不产生空隙。该方法可以包括提供衬底，在衬底上形成虚拟栅电极，在衬底上形成与虚拟栅电极相邻的栅极间隔物，通过同时去除虚设栅电极的一部分形成第一凹槽，所述第一凹部具有比下端更宽的上端，通过去除在形成所述第一凹部之后残留的所述虚设栅电极形成第二凹槽，以及通过沉积金属以填充所述第一凹部而形成金属栅电极，以填充所述第一凹部第二个凹槽

24. 发明申请

US20130023118A1 METHOD FOR FORMING PATTERN AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：用于形成图案的方法和使用其制造半导体器件的方法
公开(公告)号：US20130023118A1
公开(公告)日：2013-01-24
申请号：US13493321
申请日：2012-06-11
申请人： Soo-Yeon Jeong , Dong-Kwon Kim , Do-Hyoung Kim , Myeong-Cheol Kim
发明人： Soo-Yeon Jeong , Dong-Kwon Kim , Do-Hyoung Kim , Myeong-Cheol Kim
IPC分类号： H01L21/311 , H01L21/768
CPC分类号： H01L21/31144 , H01L21/76811 , H01L21/76816
摘要： There is provided a method for forming a pattern comprising, forming a first layer on an underlying layer including a substrate, forming a first mask pattern including a first opening pattern on the first layer, and forming a second mask pattern including a second opening pattern on the first mask pattern, wherein the second opening pattern includes a first region overlapping the first opening pattern and a second region not overlapping the first opening pattern, and etching is performed using the second mask pattern such that a third opening pattern corresponding to the first region and exposing an upper surface of the underlying layer is formed in the first layer, and a fourth opening pattern corresponding to the second region is formed in the first mask pattern.
摘要翻译：提供了一种用于形成图案的方法，包括：在包括基底的下层上形成第一层，在第一层上形成包括第一开口图案的第一掩模图案，以及在第一层上形成包括第二开口图案的第二掩模图案第一掩模图案，其中第二开口图案包括与第一开口图案重叠的第一区域和不与第一开口图案重叠的第二区域，并且使用第二掩模图案进行蚀刻，使得对应于第一开口图案的第一开口图案并且在第一层中形成下面的层的上表面，并且在第一掩模图案中形成与第二区域对应的第四开口图案。

25. 发明申请

US20120135577A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120135577A1
公开(公告)日：2012-05-31
申请号：US13304936
申请日：2011-11-28
申请人： Doo-Young LEE , Ki Il Kim , Myeong-Cheol Kim , Do-Hyoung Kim , Do-Hsing Lee
发明人： Doo-Young LEE , Ki Il Kim , Myeong-Cheol Kim , Do-Hyoung Kim , Do-Hsing Lee
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/78 , H01L21/76829 , H01L21/76832 , H01L21/76895 , H01L21/76897 , H01L29/66545
摘要： A method of manufacturing a semiconductor device, including the second sacrificial layer receiving a gate structure include a metal and a spacer on a sidewall of the gate structure therethrough being formed on a substrate. The second sacrificial layer is removed. A second etch stop layer and an insulating interlayer are sequentially formed on the gate structure, the spacer and the substrate. An opening passing through the insulating interlayer is formed to expose a portion of the gate structure, a portion of the spacer and a portion of the second etch stop layer on a portion of the substrate. The second etch stop layer being exposed through the opening is removed. The contact being electrically connected to the gate structure and the substrate and filling the opening is formed. The semiconductor device having the metal gate electrode and the shared contact has a desired leakage current characteristic and resistivity characteristics.
摘要翻译：包括接收栅极结构的第二牺牲层的半导体器件的制造方法包括在基板上形成的栅极结构的侧壁上的金属和间隔物。去除第二牺牲层。在栅极结构，间隔物和衬底上依次形成第二蚀刻停止层和绝缘中间层。形成通过绝缘中间层的开口以暴露栅极结构的一部分，间隔物的一部分和第二蚀刻停止层的一部分在衬底的一部分上。去除通过开口露出的第二蚀刻停止层。形成与栅极结构和基板电连接并填充开口的触点。具有金属栅电极和共用触点的半导体器件具有期望的漏电流特性和电阻率特性。

26. 发明申请

US20120088359A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120088359A1
公开(公告)日：2012-04-12
申请号：US13242382
申请日：2011-09-23
申请人： Dong-Kwon Kim , Young-Ju Park , Dong-Hyuk Yeam , Yoo-Jung Lee , Myeong-Cheol Kim , Do-Hyoung Kim , Heung-Sik Park
发明人： Dong-Kwon Kim , Young-Ju Park , Dong-Hyuk Yeam , Yoo-Jung Lee , Myeong-Cheol Kim , Do-Hyoung Kim , Heung-Sik Park
IPC分类号： H01L21/336
CPC分类号： H01L21/28132 , H01L21/28114 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/6656
摘要： Example embodiments relate to a method for manufacturing a semiconductor device, wherein a metal gate electrode therein may be formed without a void in a lower portion of the metal gate electrode. The method may include providing a substrate, forming a dummy gate electrode on the substrate, forming a gate spacer on the substrate to be contiguous to the dummy gate electrode, forming a first recess by simultaneously removing a portion of the dummy gate electrode and a portion of the gate spacer, the first recess having an upper end wider than a lower end, forming a second recess by removing the dummy gate electrode remaining after forming the first recess, and forming a metal gate electrode by depositing a metal to fill the first and second recesses.
摘要翻译：示例性实施例涉及用于制造半导体器件的方法，其中可以在金属栅电极的下部中形成其中的金属栅极电极，而不产生空隙。该方法可以包括提供衬底，在衬底上形成虚拟栅电极，在衬底上形成与虚拟栅电极相邻的栅极间隔物，通过同时去除虚拟栅电极的一部分形成第一凹槽，所述第一凹部具有比下端更宽的上端，通过去除在形成所述第一凹部之后残留的所述虚设栅电极形成第二凹槽，以及通过沉积金属以填充所述第一凹部而形成金属栅电极，以填充所述第一凹部第二个凹槽

27. 发明申请

US20100298149A1 COMBINATION TWIST STRUCTURE OF THE SUPER CONDUCTION CABLE 审中-公开
标题翻译：超导体电缆的组合结构
公开(公告)号：US20100298149A1
公开(公告)日：2010-11-25
申请号：US12518353
申请日：2007-12-27
申请人： Do-Hyoung Kim , Choon-Dong Kim , Hyun-Man Jang , In-Son Park , Bong-Ki Ji , Nam-Yul Kim
发明人： Do-Hyoung Kim , Choon-Dong Kim , Hyun-Man Jang , In-Son Park , Bong-Ki Ji , Nam-Yul Kim
IPC分类号： H01B12/10 , H01B12/00
CPC分类号： H01B12/02 , Y02E40/641
摘要： The present invention relates to a combination twist structure of a superconducting cable core. The present invention relates to a new type of a combination twist structure of a superconducting cable core capable of accommodating the thermal contraction of the cable core in the longitudinal direction without having a space for accommodation, thereby capable of reducing an outer diameter of the superconducting cable, and eliminating the use of an additional equipment for forming the space for accommodation. The present invention provides a combination twist structure of a superconducting cable core formed by twisting a plurality of cable cores. The cable cores are combined by repeatedly changing a twist direction of the cable cores, and the contraction of the cable cores in the longitudinal direction is accommodated by untwisting the cable cores.
摘要翻译：本发明涉及超导电缆芯的组合扭转结构。本发明涉及一种新型的超导电缆芯的组合扭转结构，其能够在纵向方向上容纳电缆芯的热收缩，而不具有用于容纳的空间，从而能够减小超导电缆的外径，并且消除了使用附加设备来形成住宿空间。本发明提供了通过扭绞多根电缆芯形成的超导电缆芯的组合扭转结构。通过重复地改变电缆芯的扭转方向来组合电缆芯，并且通过解开电缆芯来解决电缆芯在纵向上的收缩。

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