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21. 发明申请

US20070174803A1 Method for concurrent search and select of routing patterns for a routing system 审中-公开
标题翻译：路由系统的并发搜索和路由选择模式的方法
公开(公告)号：US20070174803A1
公开(公告)日：2007-07-26
申请号：US11651458
申请日：2007-01-10
申请人： Jung-Cheun Lien , Minchen Zhao
发明人： Jung-Cheun Lien , Minchen Zhao
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method for concurrent search and select of routing patterns for a routing system is provided. The provided method introduces a metric for indicating the goodness of a routing pattern for guiding the selection of search engine at the route finding stage. Next, the method explores routes based on a plurality of feasible routing track segments that represent the longest continuous span of possible routes on a routing layer. Next, the preferred routing patterns can be selected. After that, the method goes to find one or more routing violations and then avoid the routing violations. Furthermore, the avoidance of the routing violation(s) can be implemented by reducing the length of the feasible routing track segment, or removing portion of a routed segment running in parallel and adjacent track(s) of the feasible routing track segment.
摘要翻译：提供了用于并行搜索和路由选择路由选择的方法。所提供的方法引入用于指示路由模式的优点的度量，用于在路线发现阶段指导搜索引擎的选择。接下来，该方法基于表示路由层上可能路由的最长连续跨度的多个可行路由轨道段来探索路由。接下来，可以选择优选的路由模式。之后，该方法会发现一个或多个路由违规，然后避免路由违规。此外，可以通过减少可行路由轨道段的长度或者去除在可行路由轨道段的并行和相邻轨道中运行的路由段的部分来实现路由违规的避免。

22. 发明申请

US20070106971A1 Apparatus for a routing system 审中-公开
标题翻译：路由系统设备
公开(公告)号：US20070106971A1
公开(公告)日：2007-05-10
申请号：US11590765
申请日：2006-11-01
申请人： Jung-Cheun Lien , Minchen Zhao
发明人： Jung-Cheun Lien , Minchen Zhao
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： The invention details methods and apparatus for a routing system or router that includes a model. The model can be in many different forms including but not limited to: resolution enhancement technologies such as OPC; lithography model including but not limited to aerial image; pattern-dependent functions; functions for timing/signal integrity/power; manufacturing process variations; and measured silicon data. In one embodiment, the model can be described as input to the system and the model calculator can interact either with the data structure or the query engine of the detail router or both. The model calculator can accept input as a set of geometry description and produce output to guide the query functions. An example technique called set intersection is disclosed herein to combine multiple models in the system. A preferred embodiment of this invention includes a full chip grid-based router being aware of manufacturability.
摘要翻译：本发明详细描述了包括模型的路由系统或路由器的方法和装置。该模型可以有许多不同的形式，包括但不限于：分辨率增强技术，如OPC; 光刻模型包括但不限于航空图像; 模式相关函数; 定时/信号完整性/功率的功能; 制造工艺变化; 并测量硅数据。在一个实施例中，该模型可以被描述为对系统的输入，并且模型计算器可以与详细路由器的数据结构或查询引擎或两者交互。模型计算器可以接受输入作为一组几何描述并产生输出来指导查询功能。本文公开了一种称为集合交集的示例性技术来组合系统中的多个模型。本发明的一个优选实施例包括一个意识到可制造性的全芯片基于网格的路由器。

23. 发明授权

US06968487B1 User available body scan chain 有权
标题翻译：用户可用的身体扫描链
公开(公告)号：US06968487B1
公开(公告)日：2005-11-22
申请号：US10071262
申请日：2002-02-07
申请人： Ian Bryant , Chung-Yuan Sun , Sheng Feng , Jung-Cheun Lien , Stephen Chan
发明人： Ian Bryant , Chung-Yuan Sun , Sheng Feng , Jung-Cheun Lien , Stephen Chan
IPC分类号： H03K19/177 , G01R31/28 , G06G7/48 , H03K17/693
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： A method of accessing the testing means in a Field Programmable Gate Array (“FPGA”) comprised of a plurality of functional groups (“FGs”) comprising: inputting a function netlist defining a user circuit; compiling said function netlist; and generating a logic Built-In Self Test (“BIST”) netlist; wherein said BIST netlist replaces all user registers with scan registers with a scan chain routed as the physical silicon scan chains.
摘要翻译：一种在由多个功能组（“FG”）组成的现场可编程门阵列（“FPGA”）中访问测试装置的方法，包括：输入定义用户电路的功能网表; 编译功能网表; 并生成逻辑内置自检（“BIST”）网表; 其中所述BIST网表用扫描链替换具有扫描寄存器的所有用户寄存器，所述扫描链作为物理硅扫描链路由。

24. 发明授权

US06774670B1 Intra-tile buffer system for a field programmable gate array 有权
标题翻译：用于现场可编程门阵列的片内缓冲系统
公开(公告)号：US06774670B1
公开(公告)日：2004-08-10
申请号：US10334340
申请日：2002-12-30
申请人： Sheng Feng , Tong Liu , Jung-Cheun Lien
发明人： Sheng Feng , Tong Liu , Jung-Cheun Lien
IPC分类号： H03K19177
CPC分类号： H03K19/17736
摘要： The invention relates to an intra-tile buffering system for a field programmable gate array. The field programmable gate array comprises a field programmable gate array tile comprising a number of rows and a number of columns. Each row has a left end and a right end, and each column has a top end and a bottom end. Each row comprises a plurality of functional groups with an interface group located at said right end and said left end. Each column comprises a plurality of functional groups with an interface group located at said top end and said bottom end. A primary routing structure is coupled to said functional groups and interface groups and configured to receive primary output signals, route primary output signals within said at least one field programmable gate array tile, and provide primary input signals to said functional groups and interface groups. Each functional group is configured to receive a primary input signal, perform a logic operation, and generate a primary output signal. Each interface group is configured to transfer signals from said primary routing structure to outside of said at least one field programmable gate array tile, and includes a plurality of input multiplexers configured to select signals received from outside of said at least one field programmable gate array tile and provide signals to the primary routing structure inside said at least one field programmable gate array tile. Said primary routing structure comprises a horizontal bus coupled to each row of functional groups, a vertical bus coupled to each column of functional groups, a horizontal buffer coupled to each horizontal bus and spaced every Nth column of functional groups, where N is an integer, and a vertical buffer coupled to each horizontal bus and spaced every Mth row of functional groups, where M is an integer.
摘要翻译：本发明涉及用于现场可编程门阵列的片内缓冲系统。现场可编程门阵列包括包括多行和多列的现场可编程门阵列瓦片。每排具有左端和右端，每列具有顶端和底端。每行包括具有位于所述右端和所述左端的界面组的多个功能组。每列包括具有位于所述顶端和所述底端的界面组的多个官能团。主路由结构耦合到所述功能组和接口组，并被配置为接收主输出信号，在所述至少一个现场可编程门阵列瓦片内路由主输出信号，并向所述功能组和接口组提供初级输入信号。每个功能组被配置为接收主输入信号，执行逻辑运算并产生主输出信号。每个接口组被配置为将信号从所述主路由结构传送到所述至少一个现场可编程门阵列瓦片外部，并且包括多个输入多路复用器，其被配置为选择从所述至少一个现场可编程门阵列瓦片外部接收的信号并向所述至少一个现场可编程门阵列瓦片内的主路由结构提供信号。所述主路由结构包括耦合到每行功能组的水平总线，耦合到每个功能组列的垂直总线，耦合到每个水平总线的水平缓冲器，并且每N个第N列的功能组间隔开，其中N是整数，以及垂直缓冲器，其耦合到每个水平总线并且每隔第M行排列的功能组，其中M是整数。

25. 发明授权

US06700404B1 Tileable field-programmable gate array architecture 有权
标题翻译：可拼接现场可编程门阵列架构
公开(公告)号：US06700404B1
公开(公告)日：2004-03-02
申请号：US10066398
申请日：2002-01-30
申请人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
发明人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
IPC分类号： H03K19177
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside of the first FPGA tile.
摘要翻译：一种装置包括现场可编程门阵列（FPGA）。所述FPGA包括第一FPGA瓦片，并且所述第一FPGA瓦片除了第一组路由导体和第二组布线导体以及多个布线导体之外，还包括多个功能组（FG），第三组布线导体接口组（IG）。多个FG布置成行和列，其中每个FG被配置为接收三次输入信号以及常规输入信号，执行逻辑运算并产生常规输出信号。第三组路由导体被耦合到FG的第一组输出端口并且被配置为接收信号，在第一FPGA瓦片内路由信号，并且向FG的第三组输入端口提供输入信号。多个IG围绕多个FG，使得一个IG位于每行和每列的每一端。每个IG耦合到第三组路由导体并且被配置为将信号从第三组路由导体传送到第一FPGA片外部。

26. 发明授权

US06611153B1 Tileable field-programmable gate array architecture 失效
公开(公告)号：US06611153B1
公开(公告)日：2003-08-26
申请号：US10061955
申请日：2002-01-31
申请人： Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao
发明人： Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao
IPC分类号： H03K19177
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The routability of the regular routing structure is maximized by depositing switches according to designators. This novel designation method provides the same routability with approximately half the switches. Thus, further reduction in routing area is achieved. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile.

27. 发明授权

US06870396B2 Tileable field-programmable gate array architecture 有权
标题翻译：可拼接现场可编程门阵列架构
公开(公告)号：US06870396B2
公开(公告)日：2005-03-22
申请号：US10429004
申请日：2003-04-30
申请人： Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao
发明人： Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17732
摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The routability of the regular routing structure is maximized by depositing switches according to designators. This novel designation method provides the same routability with approximately half the switches. Thus, further reduction in routing area is achieved. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile.
摘要翻译：一种装置包括现场可编程门阵列（FPGA）。 FPGA包括第一FPGA片，并且第一FPGA片包括多个功能组（FG），规则路由结构以及多个接口组（IG）。多个FG布置成行和列，其中每个FG被配置为接收常规输入信号，执行逻辑运算并产生规则的输出信号。常规路由结构耦合到FG并被配置成接收常规输出信号，在第一FPGA片内路由信号，并向FG提供常规输入信号。通过根据指示符存放交换机来最大化常规路由结构的可路由性。这种新颖的指定方法与大约一半的开关提供相同的可路由性。因此，实现了路由区域的进一步减少。多个IG围绕多个FG，使得一个IG位于每行和每列的每一端。每个IG耦合到常规路由结构并且被配置为将信号从常规路由结构传送到第一FPGA块的外部。

28. 发明授权

US06800884B1 Inter-tile buffer system for a field programmable gate array 有权
标题翻译：用于现场可编程门阵列的片间缓冲系统
公开(公告)号：US06800884B1
公开(公告)日：2004-10-05
申请号：US10334393
申请日：2002-12-30
申请人： Sheng Feng , Tong Liu , Jung-Cheun Lien
发明人： Sheng Feng , Tong Liu , Jung-Cheun Lien
IPC分类号： H01L2710
CPC分类号： H03K19/17736 , H01L27/118
摘要： The invention relates to an inter-tile buffering system for a field programmable gate array. The field programmable gate array is comprised of the following. A plurality of field programmable gate array tiles are arranged in an array of rows and columns. Each of said field programmable gate array tiles comprises a plurality of functional groups and a plurality of interface groups, and a primary routing structure. The primary routing structure is coupled to said functional groups and interface groups and is configured to receive primary output signals, route primary output signals within said at least one field programmable gate array tile, and provide primary input signals to said functional groups and interface groups. Each functional group is configured to receive primary input signals, perform a logic operation, and generate primary output signals. Each interface group is configured to transfer signals from said primary routing structure to outside of said at least one field programmable gate array tile, and includes a plurality of input multiplexers configured to select signals received from outside of said at least one field programmable gate array tile and provide signals to the primary routing structure inside said at least one field programmable gate array tile. Said primary routing structure comprises a horizontal bus and a vertical bus. A horizontal buffer is located between each column of field programmable gate array tiles and is coupled to the primary routing structure. A vertical buffer is located between each row of field programmable gate array tiles and is coupled to the primary routing structure.
摘要翻译：本发明涉及一种用于现场可编程门阵列的块间缓冲系统。现场可编程门阵列由以下组成。多个现场可编程门阵列瓦片被布置成行和列的阵列。每个所述现场可编程门阵列瓦片包括多个功能组和多个接口组以及主要路由结构。主路由结构耦合到所述功能组和接口组，并被配置为接收主要输出信号，在所述至少一个现场可编程门阵列瓦片内路由主输出信号，并向所述功能组和接口组提供初级输入信号。每个功能组被配置为接收主要输入信号，执行逻辑运算并产生主要输出信号。每个接口组被配置为将信号从所述主路由结构传送到所述至少一个现场可编程门阵列瓦片外部，并且包括多个输入多路复用器，其被配置为选择从所述至少一个现场可编程门阵列瓦片外部接收的信号并向所述至少一个现场可编程门阵列瓦片内的主路由结构提供信号。所述主路由结构包括水平总线和垂直总线。水平缓冲器位于每列现场可编程门阵列瓦片之间，并耦合到主路由结构。垂直缓冲器位于每行现场可编程门阵列瓦片之间，并耦合到主路由结构。

29. 发明授权

US06744278B1 Tileable field-programmable gate array architecture 有权
公开(公告)号：US06744278B1
公开(公告)日：2004-06-01
申请号：US10061951
申请日：2002-01-31
申请人： Tong Liu , Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Naihui Liao
发明人： Tong Liu , Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Naihui Liao
IPC分类号： H03K19177
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside of the first FPGA tile.

30. 发明授权

US06731133B1 Routing structures for a tileable field-programmable gate array architecture 有权
标题翻译：用于瓦片现场可编程门阵列架构的路由结构
公开(公告)号：US06731133B1
公开(公告)日：2004-05-04
申请号：US10077190
申请日：2002-02-15
申请人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao
发明人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao
IPC分类号： H03K19177
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： A field-programmable gate array (FPGA), comprising: a first FPGA tile, the first FPGA tile comprising a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile. The first FPGA tile also comprising a secondary routing structure independent of the regular routing structure, coupled to each of the IGs, configured to transfer signals from said first FPGA tile to at least one other FPGA tile. The disclosed apparatus also provides for a routing structure between IGs and RAM blocks. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understand that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：一种现场可编程门阵列（FPGA），包括：第一FPGA片，所述第一FPGA片包括多个功能组（FG），规则路由结构以及多个接口组（IG）。多个FG布置成行和列，其中每个FG被配置为接收常规输入信号，执行逻辑运算并产生规则的输出信号。常规路由结构耦合到FG并被配置成接收常规输出信号，在第一FPGA片内路由信号，并向FG提供常规输入信号。多个IG围绕多个FG，使得一个IG位于每行和每列的每一端。每个IG耦合到常规路由结构并且被配置为将信号从常规路由结构传送到第一FPGA块的外部。第一FPGA片还包括独立于常规路由结构的辅路由结构，耦合到每个IG，被配置为将信号从所述第一FPGA片传送到至少另一个FPGA片。所公开的装置还提供了IG和RAM块之间的路由结构。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交的理由是，它不会用于解释或限制权利要求的范围或含义。

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