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    • 24. 发明申请
    • Closed-grid bus architecture for wafer interconnect structure
    • 晶圆互连结构的闭路总线架构
    • US20050001638A1
    • 2005-01-06
    • US10832700
    • 2004-04-27
    • Charles MillerJohn Long
    • Charles MillerJohn Long
    • G01R1/073H05K1/00H05K1/02G01R31/02
    • G01R31/31926G01R1/07378G01R31/318511G11C29/56G11C2029/2602H05K1/0216H05K1/023H05K1/0289H05K2201/09254Y10T29/49117
    • An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.
    • 互连结构采用闭合栅格总线将集成电路测试器通道连接到半导体晶片上的输入/输出(I / O)焊盘阵列,使得测试仪通道可以同时与所有I / O焊盘通信。 互连结构包括实现总线节点阵列的电路板,每个总线节点对应于单独的一个I / O焊盘。 电路板包括至少两层。 安装在第一层上的轨迹形成一组第一个菊花链总线,每个链路总线连接总线节点阵列的单独行的所有总线节点。 安装在第二电路板层上的迹线形成一组第二菊花链总线,每条链路总线连接总线节点阵列的单独列的所有总线节点。 第一和第二菊花链总线的通路和其他电路板互连端,使得它们形成闭合栅格总线。 每个总线节点通过单独的隔离电阻器连接到安装在电路板表面上的单独的接触焊盘。 一组弹簧触点或探针将每个接触垫连接到晶片上的单独的I / O焊盘之间。
    • 26. 发明授权
    • Method and apparatus for terminating a test signal applied to multiple semiconductor loads under test
    • 用于终止应用于被测试的多个半导体负载的测试信号的方法和装置
    • US08098076B2
    • 2012-01-17
    • US12416375
    • 2009-04-01
    • Guang ChenCharles MillerDavid Pritzkau
    • Guang ChenCharles MillerDavid Pritzkau
    • G01R31/20
    • G01R31/31905
    • Apparatus for terminating a test signal applied to multiple semiconductor loads under test is described—for example apparatus for interfacing a test signal between a tester and a semiconductor device under test (DUT). In some examples, a probe card assembly may include at least one probe substrate each having test probes configured to contact test features of a DUT; a wiring substrate, coupled to the at least one probe substrate, having a connector configured for coupling with a source termination of a tester; a signal path formed on and/or in the wiring substrate and the at least one probe substrate, the signal path having a trace and trace stubs fanning out from the trace, an input of the trace being coupled to the connector and outputs of the trace stubs being coupled to the test probes; and a resistive termination coupled between the trace and at least one potential.
    • 描述了用于终止施加到被测试的多个半导体负载的测试信号的装置,例如用于在测试器和待测半导体器件(DUT)之间接合测试信号的装置。 在一些示例中,探针卡组件可以包括至少一个探针基板,每个探针基板具有被配置为接触DUT的测试特征的测试探针; 耦合到所述至少一个探针衬底的布线衬底,具有被配置为与测试器的源端接耦合的连接器; 形成在布线基板和至少一个探针基板上和/或布线基板和至少一个探针基板上的信号路径,该信号路径具有从迹线扇出的迹线和迹线短线,迹线的输入耦合到连接器和迹线的输出 桩被耦合到测试探针; 以及耦合在迹线和至少一个电位之间的电阻终端。