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21. 发明授权

US09496274B2 Three-dimensional non-volatile memory device 有权
标题翻译：三维非易失性存储器件
公开(公告)号：US09496274B2
公开(公告)日：2016-11-15
申请号：US14264407
申请日：2014-04-29
申请人： SanDisk Technologies, Inc.
发明人： Jayavel Pachamuthu , Johann Alsmeier , Raghuveer S. Makala , Yao-Sheng Lee
IPC分类号： H01L21/8246 , H01L21/8247 , H01L27/115 , H01L27/105 , H01L21/02 , H01L27/112 , H01L27/06 , H01L27/10 , H01L29/66 , H01L29/792 , H01L21/306
CPC分类号： H01L27/11551 , H01L21/022 , H01L21/30604 , H01L27/0688 , H01L27/101 , H01L27/1052 , H01L27/1128 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7926
摘要： A memory device includes a stack of material layers with a plurality of NAND strings extending through the stack, and a trench through the stack with a pair of sidewalls defining a width of the trench that is substantially constant or decreases from the top of the trench to a first depth and increases between a first depth and a second depth that is closer to the bottom of the trench than the first depth and the trench has an insulating material covering at least the trench sidewalls. Further embodiments include a memory device including a stack of material layers and an active memory cell region defined between a pair of trenches, and within the active region the stack comprises alternating layers of a first material and a second material, and outside of the active region the stack comprises alternating layers of the first material and a third material.
摘要翻译：存储器件包括具有延伸穿过堆叠的多个NAND串的材料层堆叠以及穿过堆叠的沟槽，该沟槽具有限定沟槽宽度的一对侧壁，所述沟槽的宽度从沟槽的顶部基本上恒定或减小，在比第一深度更靠近沟槽底部的第一深度和第二深度之间增加第一深度并且沟槽具有覆盖至少沟槽侧壁的绝缘材料。另外的实施例包括存储器件，其包括堆叠的材料层和限定在一对沟槽之间的有源存储器单元区域，并且在有源区域内，堆叠包括第一材料和第二材料的交替层，以及活性区域外堆叠包括第一材料和第三材料的交替层。

22. 发明授权

US09449981B2 Three dimensional NAND string memory devices and methods of fabrication thereof 有权
标题翻译：三维NAND串存储器件及其制造方法
公开(公告)号：US09449981B2
公开(公告)日：2016-09-20
申请号：US14520084
申请日：2014-10-21
申请人： SanDisk Technologies, Inc.
发明人： Jayavel Pachamuthu , Johann Alsmeier , Henry Chien
IPC分类号： H01L21/336 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/788 , H01L21/311 , H01L21/02 , H01L21/285 , H01L21/28
CPC分类号： H01L27/11556 , H01L21/02164 , H01L21/0217 , H01L21/02244 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/02667 , H01L21/02672 , H01L21/28273 , H01L21/28282 , H01L21/28556 , H01L21/28568 , H01L21/31111 , H01L27/11524 , H01L27/1157 , H01L27/11582 , H01L29/42328 , H01L29/42344 , H01L29/4916 , H01L29/4966 , H01L29/7883
摘要： A method includes forming an amorphous or polycrystalline semiconductor material over at least a portion of a sidewall of a front side opening and within front side recesses in a stack of alternating first and second material layers, forming a layer of a metal material over at least a portion of the sidewall of the front side opening and adjacent to the semiconductor material within the front side recesses; annealing the metal material and the semiconductor material within the front side recesses to form a large grain polycrystalline or single crystal semiconductor material charge storage region within each of the front side recesses by a metal induced crystallization process, and forming a tunnel dielectric layer and semiconductor channel in the front side opening. Following the metal induced crystallization process, at least a portion of the metal material is located between the charge storage regions and the second material layers.
摘要翻译：一种方法包括在前侧开口的侧壁的至少一部分上和在交替的第一和第二材料层的堆叠中的前侧凹槽内形成非晶或多晶半导体材料，在至少一个所述前侧开口的侧壁部分与所述前侧凹部内的所述半导体材料相邻; 使金属材料和前侧凹部内的半导体材料退火，通过金属诱导结晶化工艺在每个前侧凹部内形成大晶粒多晶或单晶半导体材料电荷存储区，形成隧道电介质层和半导体沟道在前侧开口。在金属诱导结晶过程之后，金属材料的至少一部分位于电荷存储区域和第二材料层之间。

23. 发明授权

US09425299B1 Three-dimensional memory device having a heterostructure quantum well channel 有权
标题翻译：具有异质结构量子阱通道的三维存储器件
公开(公告)号：US09425299B1
公开(公告)日：2016-08-23
申请号：US14733244
申请日：2015-06-08
申请人： SANDISK TECHNOLOGIES INC.
发明人： Peter Rabkin , Jayavel Pachamuthu , Johann Alsmeier , Masaaki Higashitani
IPC分类号： H01L29/778 , H01L27/115 , H01L29/205 , H01L29/51 , H01L29/78
CPC分类号： H01L29/7783 , H01L21/28282 , H01L27/1157 , H01L27/11582 , H01L29/205 , H01L29/513 , H01L29/7787 , H01L29/7789 , H01L29/7833 , H01L29/7889
摘要： A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through a plurality of electrically conductive layers comprising control gate electrodes. A memory film in a memory opening is interposed between the vertical semiconductor channel and the electrically conductive layers. The vertical semiconductor channel includes a wider band gap semiconductor material and a narrow band gap semiconductor material. The cylindrical confinement electron gas is formed at an interface between the wider band gap semiconductor material and the narrow band gap semiconductor material. As a two-dimensional electron gas, the cylindrical confinement electron gas can provide high charge carrier mobility for the vertical semiconductor channel, which can be advantageously employed to provide higher performance for a three-dimensional memory device.
摘要翻译：限制在二维圆柱形区域内的圆柱形约束电子气体可以形成在延伸穿过包括控制栅电极的多个导电层的垂直半导体沟道中。存储器开口中的记忆膜插入在垂直半导体沟道和导电层之间。垂直半导体沟道包括较宽的带隙半导体材料和窄带隙半导体材料。在较宽带隙半导体材料和窄带隙半导体材料之间的界面处形成圆柱形约束电子气。作为二维电子气体，圆柱形约束电子气体可以为垂直半导体通道提供高电荷载流子迁移率，其可有利地用于为三维存储器件提供更高的性能。

24. 发明申请

US20160141294A1 THREE-DIMENSIONAL MEMORY STRUCTURE WITH MULTI-COMPONENT CONTACT VIA STRUCTURE AND METHOD OF MAKING THEREOF 有权
标题翻译：通过结构与多组分接触的三维存储结构及其制备方法
公开(公告)号：US20160141294A1
公开(公告)日：2016-05-19
申请号：US14926347
申请日：2015-10-29
申请人： SANDISK TECHNOLOGIES INC.
发明人： Somesh Peri , Sateesh Koka , Raghuveer S. Makala , Rahul Sharangpani , Matthias Baenninger , Jayavel Pachamuthu , Johann Alsmeier
IPC分类号： H01L27/115 , H01L29/66 , H01L29/792
CPC分类号： H01L27/1157 , H01L21/28512 , H01L21/28562 , H01L21/28568 , H01L21/76877 , H01L23/53266 , H01L27/11582 , H01L29/66553 , H01L29/78
摘要： A contact via structure can include a ruthenium portion formed by selective deposition of ruthenium on a semiconductor surface at the bottom of a contact trench. The ruthenium-containing portion can reduce contact resistance at the interface with an underlying doped semiconductor region. At least one conductive material portion can be formed in the remaining volume of the contact trench to form a contact via structure. Alternatively or additionally, a contact via structure can include a tensile stress-generating portion and a conductive material portion. In case the contact via structure is formed through an alternating stack of insulating layers and electrically conductive layers that include a compressive stress-generating material, the tensile stress-generating portion can at least partially cancel the compressive stress generated by the electrically conductive layers. The conductive material portion of the contact via structure can include a metallic material or a doped semiconductor material.
摘要翻译：接触通孔结构可以包括通过在接触沟槽的底部的半导体表面上选择性沉积钌而形成的钌部分。含钌部分可以降低与下掺杂半导体区域的界面处的接触电阻。可以在接触沟槽的剩余容积中形成至少一个导电材料部分以形成接触通孔结构。或者或另外，接触通孔结构可以包括拉伸应力产生部分和导电材料部分。在接触通孔结构通过绝缘层的交替堆叠和包括压缩应力产生材料的导电层形成的情况下，拉伸应力产生部分可以至少部分地抵消由导电层产生的压缩应力。接触通孔结构的导电材料部分可以包括金属材料或掺杂的半导体材料。

25. 发明授权

US09331093B2 Three dimensional NAND device with silicon germanium heterostructure channel 有权
标题翻译：具有硅锗异质结构通道的三维NAND器件
公开(公告)号：US09331093B2
公开(公告)日：2016-05-03
申请号：US14505870
申请日：2014-10-03
申请人： SANDISK TECHNOLOGIES INC.
发明人： Peter Rabkin , Jayavel Pachamuthu
IPC分类号： H01L27/115 , H01L29/165 , H01L29/167 , H01L29/04 , H01L21/28 , H01L21/02 , H01L29/10 , H01L29/78 , H01L29/66
CPC分类号： H01L21/28273 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02667 , H01L21/02686 , H01L21/28282 , H01L27/11556 , H01L27/11582 , H01L29/04 , H01L29/1054 , H01L29/165 , H01L29/167 , H01L29/66825 , H01L29/66833 , H01L29/7842 , H01L29/7881 , H01L29/7926
摘要： A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming an at least one opening in the stack, forming at least a portion of a memory film in the at least one opening and forming a first portion of a semiconductor channel followed by forming a second portion of the semiconductor channel in the at least one opening. The second portion of the semiconductor channel comprises silicon and germanium and contains more germanium than a first portion of the semiconductor channel which is located closer to the memory film than the second portion.
摘要翻译：一种制造单片三维NAND串的方法，包括在衬底上形成第一材料和不同于第一材料的第二材料的交替层的堆叠，在堆叠中形成至少一个开口，形成至少一部分在所述至少一个开口中的记忆膜，并形成半导体通道的第一部分，随后在所述至少一个开口中形成所述半导体通道的第二部分。半导体通道的第二部分包括硅和锗，并且比与第二部分更靠近存储膜的位于半导体通道的第一部分相比包含更多的锗。

26. 发明申请

US20160104715A1 MULTILEVEL MEMORY STACK STRUCTURE AND METHODS OF MANUFACTURING THE SAME 有权
公开(公告)号：US20160104715A1
公开(公告)日：2016-04-14
申请号：US14972389
申请日：2015-12-17
申请人： SANDISK TECHNOLOGIES INC.
发明人： Jayavel Pachamuthu , Johann Alsmeier , Henry Chien
IPC分类号： H01L27/115
CPC分类号： H01L27/11556 , H01L21/8221 , H01L27/0688 , H01L27/11524 , H01L27/11551 , H01L27/1157 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L27/2481 , H01L29/7926
摘要： A first stack of alternating layers including first electrically conductive layers and first electrically insulating layers is formed with first stepped surfaces and a first dielectric material portion thereupon. Dielectric pillar structures including a dielectric metal oxide can be formed through the first stepped surfaces. Lower memory openings can be formed, and filled with a disposable material or a lower memory opening structure including a lower semiconductor channel and a doped semiconductor region. At least one dielectric material layer and a second stack of alternating layers including second electrically conductive layers and second electrically insulating layers can be sequentially formed. Upper memory openings can be formed through the second stack and the at least one dielectric material layer. A memory film and a semiconductor channel can be formed after removal of the disposable material, or an upper semiconductor channel can be formed on the doped semiconductor region.

27. 发明授权

US09269446B1 Methods to improve programming of slow cells 有权
标题翻译：改善缓慢细胞编程的方法
公开(公告)号：US09269446B1
公开(公告)日：2016-02-23
申请号：US14681653
申请日：2015-04-08
申请人： SanDisk Technologies Inc.
发明人： Sagar Magia , Jagdish Sabde , Jayavel Pachamuthu , Ankitkumar Babariya
IPC分类号： G11C16/04 , G11C16/06 , G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3459 , G11C2216/14 , H01L27/11582
摘要： For a non-volatile memory device having a NAND type of architecture, techniques are presented for determining NAND strings that are slow to program. These techniques are particularly applicable to memory devices have a 3D structure, such as of BiCS type, where the slow programming can arise from defects of the spacing between the memory holes, in which the NAND strings are formed, and the local interconnects, such as for connecting common source lines and which run in a vertical direction between groups of NAND strings. The slow to program NAND strings can be recorded and this information can be used when writing data to the NAND strings. Several methods of writing data along a word line that includes such slow to program cells are described.
摘要翻译：对于具有NAND型架构的非易失性存储器件，呈现用于确定编程缓慢的NAND串的技术。这些技术特别适用于具有诸如BiCS类型的3D结构的存储器件，其中慢速编程可能由存在于其中形成NAND串的存储器孔之间的间隔的缺陷和局部互连（例如用于连接公共源极线并且在NAND串的组之间沿垂直方向运行。可以记录NAND串的编程速度慢，并且可以在将数据写入NAND串时使用该信息。描述了沿着包括这种慢速编程单元的字线写入数据的几种方法。

28. 发明授权

US09240249B1 AC stress methods to screen out bit line defects 有权
标题翻译：交流应力法筛选出位线缺陷
公开(公告)号：US09240249B1
公开(公告)日：2016-01-19
申请号：US14475138
申请日：2014-09-02
申请人： SanDisk Technologies Inc.
发明人： Jagdish Sabde , Sagar Magia , Jayavel Pachamuthu
IPC分类号： G11C11/34 , G11C29/12 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/34
CPC分类号： G11C29/025 , G11C16/0483 , G11C29/06 , G11C29/12005 , G11C2029/1204
摘要： A number of techniques for determining bit line related defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Defects related to bit line to NAND string contacts are determined by application of an AC stress mode along bit lines, followed by a defect detection operation. If the AC stress is applied to be out of phase on adjacent bit lines, this can also be used to accelerate bit line to bit line defects. The subsequent defect determination phase can include an erase operation followed a read to determine whether the NAND strings of the erased block read as erased, a process that can also be followed by a program and subsequent read to further check for defects.
摘要翻译：提出了用于确定非易失性存储器阵列中的位线相关缺陷的许多技术，其特别适用于诸如BiCS类型的3D NAND存储器。通过沿着位线施加AC应力模式来确定与NAND串触点的位线有关的缺陷，随后进行缺陷检测操作。如果交流应力施加在相邻位线上的相位异相，也可以用来加速位线到位线的缺陷。随后的缺陷确定阶段可以包括读取之后的擦除操作，以确定被擦除的块的NAND串是否被读取，还可以跟随程序和随后的读取以进一步检查缺陷。

29. 发明授权

US09236131B1 Bias to detect and prevent short circuits in three-dimensional memory device 有权
标题翻译：用于检测和防止三维存储器件短路的偏差
公开(公告)号：US09236131B1
公开(公告)日：2016-01-12
申请号：US14451223
申请日：2014-08-04
申请人： SanDisk Technologies Inc.
发明人： Jiahui Yuan , Jayavel Pachamuthu , Yingda Dong , Wei Zhao
IPC分类号： G11C16/04 , G11C16/10 , G11C16/26 , H01L21/822
CPC分类号： G11C16/10 , G11C7/12 , G11C16/24 , G11C16/26 , G11C29/021 , G11C29/025 , G11C29/028 , G11C2029/1204 , G11C2213/71 , H01L21/8221
摘要： In a three-dimensional stacked non-volatile memory device, a short circuit in a select gate layer is detected and prevented. A short circuit may occur when charges which are accumulated in select gate lines due to plasma etching, discharge through a remaining portion of the select gate layer in a short circuit path when the select gate lines are driven. To detect a short circuit, during a testing phase, an increasing bias is applied is applied to the remaining portion while a current is measured. An increase in the current above a threshold indicates that the bias has exceed a breakdown voltage of a short circuit path. A value of the bias at this time is recorded as an optimal bias. During subsequent operations involving select gate transistors or memory cells, such as programming, erasing or reading, the optimal bias is applied when the select gate lines are driven to prevent a current flow through the short circuit.
摘要翻译：在三维堆叠式非易失性存储器件中，检测并防止了选择栅极层中的短路。当选择栅极线由于等离子体蚀刻而积累的电荷，当选择栅极线被驱动时，通过选择栅极层的剩余部分在短路路径中放电，可能发生短路。为了检测短路，在测试阶段期间，在测量电流的同时，对剩余部分施加增加的偏压。高于阈值的电流的增加表明偏压已经超过短路路径的击穿电压。此时的偏差值被记录为最佳偏差。在涉及选择栅晶体管或存储单元（例如编程，擦除或读取）的后续操作期间，当驱动选择栅极线以防止电流流过短路时施加最佳偏压。

30. 发明授权

US09230982B1 Protective structure to prevent short circuits in a three-dimensional memory device 有权
标题翻译：防止三维存储器件短路的保护结构
公开(公告)号：US09230982B1
公开(公告)日：2016-01-05
申请号：US14451210
申请日：2014-08-04
申请人： SanDisk Technologies Inc.
发明人： Jiahui Yuan , Jayavel Pachamuthu , Yingda Dong , Wei Zhao
IPC分类号： H01L27/115 , H01L21/3213 , H01L27/02 , H01L27/06 , H01L29/423 , H01L21/762 , H01L49/02 , H01L29/861 , H01L29/66
CPC分类号： H01L27/11582 , G01R31/025 , G11C16/0483 , G11C29/025 , H01L21/32136 , H01L21/76224 , H01L27/0255 , H01L27/0288 , H01L27/0629 , H01L27/11519 , H01L27/11524 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L28/20 , H01L28/40 , H01L29/16 , H01L29/42328 , H01L29/42344 , H01L29/6609 , H01L29/861
摘要： In a three-dimensional stacked non-volatile memory device, a short circuit is prevented in a select gate layer by providing a protective material such as a diode, capacitor, linear resistor or varistor between select gate lines and a remaining portion of the select gate layer. Charges which are accumulated in the select gate lines due to plasma etching are therefore prevented from discharging through the remaining portion in a short circuit path when the select gate lines are driven. The protective material can comprise a p-n diode, an n-i-n or p-i-p resistor, a thin oxide layer between doped polysilicon layers in a capacitor, or a variable-resistance material such as ZnO2 between oxide layers in a varistor.
摘要翻译：在三维堆叠的非易失性存储器件中，通过在选择栅极线和选择栅极的剩余部分之间提供诸如二极管，电容器，线性电阻器或变阻器之类的保护材料，在选择栅极层中防止短路层。因此，当选择栅极线被驱动时，因此防止在等离子体蚀刻中在选择栅极线中累积的电荷通过短路路径中的剩余部分放电。保护材料可以包括p-n二极管，n-i-n或p-i-p电阻器，电容器中的掺杂多晶硅层之间的薄氧化物层，或可变电阻材料，例如可变电阻器中的氧化物层之间的ZnO 2。

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