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21. 发明授权

US5958044A Multicycle NOP 失效
标题翻译：多周期NOP
公开(公告)号：US5958044A
公开(公告)日：1999-09-28
申请号：US8909
申请日：1998-01-20
申请人： Richard A. Brown , Ray Simar , Natarajan Seshan
发明人： Richard A. Brown , Ray Simar , Natarajan Seshan
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/28
CPC分类号： G06F9/30079 , G06F9/325 , G06F9/3836 , G06F9/3838 , G06F9/3869 , G06F9/3885
摘要： A method for controlling the execution of a microprocessor to cause it to execute a NOP instruction for a programmable number of sequential cycles. A NOP instruction is provided, that includes a predetermined OP code field identifying the NOP instruction as a programmably multiple NOP instruction. A predetermined count field is provided, representing the number of sequential cycles in which a NOP operation is to be performed by said microprocessor. The NOP instruction OP code field is read, as is the NOP instruction count field. In response thereto, a NOP operation is performed for the number of sequential cycles represented by said NOP instruction count field.
摘要翻译：一种用于控制微处理器的执行以使得其执行用于可编程数量的连续循环的NOP指令的方法。提供NOP指令，其包括将NOP指令识别为可编程多个NOP指令的预定OP代码字段。提供预定的计数字段，表示由微处理器执行NOP操作的连续周期数。读取NOP指令OP代码字段，NOP指令计数字段也被读取。响应于此，对由所述NOP指令计数字段表示的连续周期数进行NOP操作。

22. 发明授权

US6081885A Method and apparatus for halting a processor and providing state visibility on a pipeline phase basis 失效
标题翻译：用于停止处理器并在流水线相位基础上提供状态可见性的方法和装置
公开(公告)号：US6081885A
公开(公告)日：2000-06-27
申请号：US974014
申请日：1997-11-19
申请人： Douglas E. Deao , Natarajan Seshan
发明人： Douglas E. Deao , Natarajan Seshan
IPC分类号： G06F9/30 , G06F9/355 , G06F9/38 , G06F11/22 , G06F11/28 , G06F11/36 , G06F11/34
CPC分类号： G06F9/3824 , G06F11/3636 , G06F11/3648 , G06F9/30072 , G06F9/30079 , G06F9/3552 , G06F9/3853 , G06F9/3875
摘要： A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline that has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Microprocessor 1 is operable to halt in response to an emulation event with partially completed instructions still in the execution pipeline. Thus, emulation unit 50 can provide visibility to the state of the microprocessor on a single pipeline phase basis. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring that could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.
摘要翻译：具有微处理器1和外围设备60-61的集成电路42上的数据处理系统设置有仿真单元50，其在连接到外部测试系统51时允许集成电路42的调试和仿真。微处理器1在指令执行管线其具有涉及获取/解码单元10a-c和功能执行单元12,14,16和18的几个执行阶段。微处理器1的流水线是不受保护的，从而可以利用数据存储器22和寄存器文件20的存储器访问等待时间存储在指令存储器23中的系统程序代码。仿真单元50提供用于模拟微处理器1的未受保护流水线并用于快速上载和下载存储器22-23的装置。微处理器1可操作以响应于具有仍处于执行流水线中的部分完成的指令的仿真事件而停止。因此，仿真单元50可以在单个流水线相位的基础上提供对微处理器的状态的可见性。仿真单元50以防止在仿真期间可能会影响存储器22-23或外围设备60-61的外来操作的方式操作。

23. 发明授权

US6065106A Resuming normal execution by restoring without refetching instructions in multi-word instruction register interrupted by debug instructions loading and processing 失效
标题翻译：通过恢复正常执行，通过在调试指令加载和处理中断的多字指令寄存器中无需重写指令进行恢复
公开(公告)号：US6065106A
公开(公告)日：2000-05-16
申请号：US974741
申请日：1997-11-19
申请人： Douglas E. Deao , Natarajan Seshan
发明人： Douglas E. Deao , Natarajan Seshan
IPC分类号： G01R31/317 , G01R31/3185 , G06F9/30 , G06F9/355 , G06F9/38 , G06F11/28 , G06F11/36 , G06F11/26
CPC分类号： G06F9/3552 , G01R31/31705 , G01R31/318566 , G06F11/362 , G06F11/3648 , G06F9/3005 , G06F9/30101 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30134 , G06F9/3842 , G06F9/3853
摘要： A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. During emulation, the fetching of instructions from program memory can be halted. A packet of instructions can be transferred from the emulation unit to the instruction register of the processor via a test port and executed without fetching instructions from instruction memory. The packet of instructions can perform various tasks, such as loading or storing data or loading new instructions into program memory. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.
摘要翻译：具有微处理器1和外围设备60-61的集成电路42上的数据处理系统设置有仿真单元50，其在连接到外部测试系统51时允许集成电路42的调试和仿真。微处理器1在指令执行管线其具有涉及获取/解码单元10a-c和功能执行单元12,14,16和18的多个执行阶段。微处理器1的流水线是不受保护的，从而可以利用数据存储器22和寄存器文件20的存储器访问等待时间存储在指令存储器23中的系统程序代码。仿真单元50提供用于模拟微处理器1的未受保护流水线并用于快速上载和下载存储器22-23的装置。在仿真期间，可以停止从程序存储器中取出指令。一组指令可以通过测试端口从仿真单元传送到处理器的指令寄存器，并在不从指令存储器中取出指令的情况下执行。指令包可以执行各种任务，例如加载或存储数据或将新指令加载到程序存储器中。仿真单元50以防止在仿真期间可能影响存储器22-23或外围设备60-61的外来操作的方式操作。

24. 发明授权

US6055628A Microprocessor with a nestable delayed branch instruction without branch related pipeline interlocks 失效
标题翻译：具有可分支延迟分支指令的微处理器，无分支相关管道互锁
公开(公告)号：US6055628A
公开(公告)日：2000-04-25
申请号：US12676
申请日：1998-01-23
申请人： Natarajan Seshan , Laurence R. Simar, Jr.
发明人： Natarajan Seshan , Laurence R. Simar, Jr.
IPC分类号： G06F9/38 , G06F9/32 , G06F15/16
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3853
摘要： A microprocessor 1 has an instruction fetch/decode unit 10a-c, a plurality of execution units, including an arithmetic and load/store unit D1, a multiplier M1, an ALU/shifter unit S1, an arithmetic logic unit ("ALU") L1, a shared multiport register file 20a from which data are read and to which data are written, and a memory 22. These units form an instruction execution pipeline that operates without interlocks so that nestable delayed branch instructions are provided. The control circuitry for the instruction execution pipeline is operable to begin processing a second branch instruction having a second target address on a pipeline phase immediately after beginning processing of a first branch instruction having a first target address. Furthermore, the control circuitry has no interlock or delay circuitry to condition processing of the second branch instruction based on processing of the first branch instruction, therefore the program counter circuitry receives the second target address on a pipeline phase immediately after receiving the first target address regardless of whether the first branch is taken or not. Thus, one instruction may be executed from the first target branch address and then the execution sequence can be preempted to the second target address.
摘要翻译：微处理器1具有指令提取/解码单元10a-c，多个执行单元，包括算术和加载/存储单元D1，乘法器M1，ALU /移位单元S1，算术逻辑单元（“ALU”） L1，从中读取数据并写入数据的共享多端口寄存器文件20a和存储器22.这些单元形成无互锁操作的指令执行流水线，从而提供可嵌套的延迟分支指令。用于指令执行流水线的控制电路可操作以在开始处理具有第一目标地址的第一分支指令之后立即开始处理在流水线相位上具有第二目标地址的第二分支指令。此外，控制电路没有互锁或延迟电路，以基于第一分支指令的处理来调节第二分支指令的处理，因此程序计数器电路在接收到第一目标地址之后立即在流水线阶段上接收第二目标地址是否采取第一个分支。因此，可以从第一目标分支地址执行一个指令，然后执行序列可以被抢占到第二目标地址。

25. 发明授权

US5970241A Maintaining synchronism between a processor pipeline and subsystem pipelines during debugging of a data processing system 失效
标题翻译：在数据处理系统调试期间，保持处理器管线和子系统管道之间的同步
公开(公告)号：US5970241A
公开(公告)日：1999-10-19
申请号：US974589
申请日：1997-11-19
申请人： Douglas E. Deao , Natarajan Seshan , Anthony J. Lell
发明人： Douglas E. Deao , Natarajan Seshan , Anthony J. Lell
IPC分类号： G06F9/38 , G06F9/30 , G06F11/00
CPC分类号： G06F11/3632 , G06F9/3869
摘要： A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.
摘要翻译：具有微处理器1和外围设备60-61的集成电路42上的数据处理系统设置有仿真单元50，其在连接到外部测试系统51时允许集成电路42的调试和仿真。微处理器1具有指令执行管线其具有涉及获取/解码单元10a-c和功能执行单元12,14,16和18的多个执行阶段。微处理器1的流水线是不受保护的，从而可以利用数据存储器22和寄存器文件20的存储器访问等待时间存储在指令存储器23中的系统程序代码。仿真单元50提供用于模拟微处理器1的未受保护流水线并用于快速上载和下载存储器22-23的装置。仿真单元50以防止在仿真期间可能影响存储器22-23或外围设备60-61的外来操作的方式操作。

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