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21. 发明申请

US20060063334A1 Fin FET diode structures and methods for building 审中-公开
标题翻译：翅片FET二极管结构和建筑方法
公开(公告)号：US20060063334A1
公开(公告)日：2006-03-23
申请号：US10944624
申请日：2004-09-17
申请人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff , Laura Zumbrunnen
发明人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff , Laura Zumbrunnen
IPC分类号： H01L21/336
CPC分类号： H01L29/861 , H01L29/785
摘要： FinFET diode structures and methods are provided for building the FinFET diode structures. A FinFET diode structure is created by implanting a diffusion Fin on a first side with a P+ dopant and on a second side with a N+ dopant providing a P+N+ diode structure.
摘要翻译： FinFET二极管结构和方法用于构建FinFET二极管结构。通过在具有P +掺杂剂的第一侧上注入扩散鳍并且在第二侧上用提供P + N +二极管结构的N +掺杂剂注入FinFET二极管结构。

22. 发明申请

US20060060926A1 Semiconductor scheme for reduced circuit area in a simplified process 失效
公开(公告)号：US20060060926A1
公开(公告)日：2006-03-23
申请号：US10944626
申请日：2004-09-17
申请人： Todd Christensen , Richard Donze , William Hovis , Terrance Kueper , John Sheets
发明人： Todd Christensen , Richard Donze , William Hovis , Terrance Kueper , John Sheets
IPC分类号： H01L29/40 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/76889 , H01L21/76895 , H01L29/458 , H01L29/785
摘要： An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.

23. 发明申请

US20050081125A1 Device having spare I/O and method of using a device having spare I/O 失效
标题翻译：具有备用I / O的设备和使用具有备用I / O的设备的方法
公开(公告)号：US20050081125A1
公开(公告)日：2005-04-14
申请号：US10675420
申请日：2003-09-30
申请人： William Cochran , William Hovis
发明人： William Cochran , William Hovis
IPC分类号： G06F11/00 , G06F11/20
CPC分类号： G06F11/1666 , G06F11/20 , G06F11/2007 , G11C29/846
摘要： A method and apparatus for correcting internally defective devices by routing signals on an I/O line to a spare internal network. Such devices enable a system designer to substitute good internal networks, e.g., memory arrays, for failing internal networks without loss of functionality at the I/O level. A device includes a plurality of I/O lines, a plurality of internal networks, a plurality of multiplexers for routing signals from the individual I/O lines to the individual internal networks, and a multiplex controller for controlling the signal routing. Routing can be performed using multiplexers that operatively interconnect any I/O line with any internal network, multiplexers that shift signals on an I/O line to and adjacent internal network, and/or multiplexers that can shift signals on an I/O through a multiplexer to any other multiplexer, and then to any internal network.
摘要翻译：一种用于通过将I / O线路上的信号路由到备用内部网络来校正内部缺陷设备的方法和装置。这样的设备使得系统设计者能够将良好的内部网络（例如，存储器阵列）替换为内部网络发生故障，而不会在I / O级别丢失功能。一种设备包括多个I / O线路，多个内部网络，用于将信号从各个I / O线路路由到各个内部网络的多路复用器，以及用于控制信号路由的多路复用控制器。可以使用将任何I / O线与任何内部网络可操作地互连的多路复用器，将I / O线上的信号转换到相邻内部网络的多路复用器和/或可以通过I / O线路移位I / O上的信号的多路复用器来执行路由。多路复用器到任何其他多路复用器，然后到任何内部网络。

24. 发明申请

US20070128740A1 Polysilicon Conductor Width Measurement for 3-Dimensional FETs 审中-公开
标题翻译：三维FET的多晶硅导体宽度测量
公开(公告)号：US20070128740A1
公开(公告)日：2007-06-07
申请号：US11670008
申请日：2007-02-01
申请人： Richard Donze , William Hovis , Terrance Kueper , John Sheets , Jon Tetzloff
发明人： Richard Donze , William Hovis , Terrance Kueper , John Sheets , Jon Tetzloff
IPC分类号： H01L21/66
CPC分类号： H01L27/1203 , H01L22/34 , H01L29/785
摘要： An apparatus and method is disclosed for determining polysilicon conductor width for 3-dimensional field effect transistors (FinFETs). Two or more resistors are constructed using a topology in which polysilicon conductors are formed over a plurality of silicon “fins”. A first resistor has a first line width. A second resistor has a second line width. The second line width is slightly different than the first line width. Advantageously, the first line width is equal to the nominal design width used to make FET gates in the particular semiconductor technology. Resistance measurements of the resistors and subsequent calculations using the resistance measurements are used to determine the actual polysilicon conductor width produced by the semiconductor process. A composite test structure not only allows calculation of the polysilicon conductor width, but provides proof that differences in the widths used in the calculations do not introduce objectionable etching characteristics of the polysilicon conductors.
摘要翻译：公开了一种用于确定三维场效应晶体管（FinFET）的多晶硅导体宽度的装置和方法。使用其中在多个硅“鳍”上形成多晶硅导体的拓扑构造两个或更多个电阻器。第一电阻器具有第一线宽度。第二电阻具有第二线宽。第二行宽度与第一行宽度略有不同。有利地，第一线宽度等于在特定半导体技术中用于制造FET栅极的标称设计宽度。电阻的电阻测量和使用电阻测量的随后的计算用于确定由半导体工艺产生的实际多晶硅导体宽度。复合测试结构不仅允许计算多晶硅导体宽度，而且提供了在计算中使用的宽度差不会引起多晶硅导体的不良刻蚀特性的证据。

25. 发明申请

US20070072385A1 Electrical Open/Short Contact Alignment Structure for Active Region vs. Gate Region 失效
公开(公告)号：US20070072385A1
公开(公告)日：2007-03-29
申请号：US11559940
申请日：2006-11-15
申请人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff
发明人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff
IPC分类号： H01L21/20 , H01L21/00 , H01L21/36
CPC分类号： H01L22/34 , H01L29/785
摘要： An apparatus and method are disclosed for measuring alignment of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias or misalignment. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the silicon area create low resistance connections between those bridging vertices and the silicon area; other bridging vertices over ROX (recessed oxide) areas do not create low resistance connections between those other bridging vertices and the silicon area. Determining which bridging vertices have low resistance connections to the silicon area and how many bridging vertices have low resistance connections to the silicon area are used to determine the bias and misalignment of the polysilicon shapes relative to the silicon area.

26. 发明申请

US20060181330A1 Method and apparatus for protecting eFuse information 失效
公开(公告)号：US20060181330A1
公开(公告)日：2006-08-17
申请号：US11060355
申请日：2005-02-17
申请人： Robert Dixon , William Hovis , Kirk Morrow
发明人： Robert Dixon , William Hovis , Kirk Morrow
IPC分类号： H01H37/76
CPC分类号： G11C17/18 , G11C16/22
摘要： A method and apparatus are provided for protecting electronic fuse (eFuse) information. A current balancing circuit is provided that maintains a constant current demand on the eFuse voltage supply that is sufficient to blow an eFuse. Normally the constant current is applied to a semiconductor core. When an eFuse is being blown, the constant current is diverted away from the core to the eFuse and as the eFuse blows, the constant current is again dumped to the semiconductor core. Thus, a change in current due to the transient of the eFuse being blown is not detectable and the information that an eFuse has been blown is kept secure.

27. 发明申请

US20060063317A1 Polysilicon conductor width measurement for 3-dimensional FETs 失效
标题翻译：三维FET的多晶硅导体宽度测量
公开(公告)号：US20060063317A1
公开(公告)日：2006-03-23
申请号：US10944622
申请日：2004-09-17
申请人： Richard Donze , William Hovis , Terrance Kueper , John Sheets , Jon Tetzloff
发明人： Richard Donze , William Hovis , Terrance Kueper , John Sheets , Jon Tetzloff
IPC分类号： H01L21/338
CPC分类号： H01L27/1203 , H01L22/34 , H01L29/785
摘要： An apparatus and method is disclosed for determining polysilicon conductor width for 3-dimensional field effect transistors (FinFETs). Two or more resistors are constructed using a topology in which polysilicon conductors are formed over a plurality of silicon “fins”. A first resistor has a first line width. A second resistor has a second line width. The second line width is slightly different than the first line width. Advantageously, the first line width is equal to the nominal design width used to make FET gates in the particular semiconductor technology. Resistance measurements of the resistors and subsequent calculations using the resistance measurements are used to determine the actual polysilicon conductor width produced by the semiconductor process. A composite test structure not only allows calculation of the polysilicon conductor width, but provides proof that differences in the widths used in the calculations do not introduce objectionable etching characteristics of the polysilicon conductors.
摘要翻译：公开了一种用于确定三维场效应晶体管（FinFET）的多晶硅导体宽度的装置和方法。使用其中在多个硅“鳍”上形成多晶硅导体的拓扑构造两个或更多个电阻器。第一电阻器具有第一线宽度。第二电阻具有第二线宽。第二行宽度与第一行宽度略有不同。有利地，第一线宽度等于在特定半导体技术中用于制造FET栅极的标称设计宽度。电阻的电阻测量和使用电阻测量的随后的计算用于确定由半导体工艺产生的实际多晶硅导体宽度。复合测试结构不仅允许计算多晶硅导体宽度，而且提供了在计算中使用的宽度差不会引起多晶硅导体的不良刻蚀特性的证据。

28. 发明申请

US20050229060A1 Method and apparatus for detecting array degradation and logic degradation 有权
标题翻译：用于检测阵列退化和逻辑劣化的方法和装置
公开(公告)号：US20050229060A1
公开(公告)日：2005-10-13
申请号：US10815248
申请日：2004-03-31
申请人： William Cochran , William Hovis
发明人： William Cochran , William Hovis
IPC分类号： G01R31/28 , G01R31/3185 , G11C17/00 , G11C29/14 , G11C29/50
CPC分类号： G11C29/50012 , G01R31/318516 , G11C29/14 , G11C29/50 , G11C2029/5004
摘要： A method and apparatus are provided for detecting degradation, such as, array degradation and logic degradation, in integrated circuits (ICs) including, for example, application specific integrated circuits (ASICs). A monitor built-in self-test (MBIST) engine is provided. At least one monitor element is coupled to the MBIST engine and is defined by predefined circuit elements in the integrated circuit. The MBIST engine is used for controlling operation of at least one monitor element for communicating with monitor bits to identify degradation of signal, timing and voltage margins.
摘要翻译：提供了一种用于在包括例如专用集成电路（ASIC）的集成电路（IC）中检测诸如阵列退化和逻辑劣化的劣化的方法和装置。提供监视器内置自检（MBIST）引擎。至少一个监视器元件耦合到MBIST引擎，并且由集成电路中的预定义的电路元件来定义。 MBIST引擎用于控制至少一个监视元件的操作，用于与监视位进行通信，以识别信号的劣化，定时和电压裕度。

29. 发明申请

US20050060629A1 Method and apparatus for implementing redundancy enhanced differential signal interface 有权
标题翻译：实现冗余增强差分信号接口的方法和装置
公开(公告)号：US20050060629A1
公开(公告)日：2005-03-17
申请号：US10660032
申请日：2003-09-11
申请人： William Cochran , William Hovis , Randall Jensen
发明人： William Cochran , William Hovis , Randall Jensen
IPC分类号： G01R31/317 , H03M13/00
CPC分类号： G01R31/31715
摘要： A method and apparatus are provided for implementing a redundancy enhanced differential signal interface. A differential signaling I/O pair is coupled to a differential receiver interface. The differential receiver interface includes a pair of multiplexers coupled to a differential receiver. An error detecting mechanism is coupled to the differential receiver for detecting an error. When an error is detected, an interface operating speed is reduced. True and complement sides of a differential signaling I/O pair are alternately tested by first enabling a multiplexer control of one of the multiplexers, reading data, and checking for the error; then enabling a multiplexer control of the other multiplexer, reading data, and checking for the error. Responsive to detecting a failure of a true side or a complement side, the detected failed true side or complement side is set to a reference voltage and the reduced interface operating speed is maintained for continued operation.
摘要翻译：提供了一种用于实现冗余增强的差分信号接口的方法和装置。差分信号I / O对耦合到差分接收器接口。差分接收器接口包括耦合到差分接收器的一对多路复用器。误差检测机构耦合到差分接收器，用于检测误差。当检测到错误时，界面操作速度降低。通过首先启用多路复用器之一的多路复用器控制，读取数据和检查错误来交替测试差分信号I / O对的真和补码侧; 然后启用另一个多路复用器的多路复用器控制，读取数据和检查错误。响应于检测真实侧或补偿侧的故障，检测到的失败的真实侧或补偿侧被设置为参考电压，并且维持降低的接口操作速度以继续操作。

30. 发明申请

US20070133333A1 EFUSE SENSE CIRCUIT 失效
标题翻译： EFUSE SENSE电路
公开(公告)号：US20070133333A1
公开(公告)日：2007-06-14
申请号：US11297311
申请日：2005-12-08
申请人： William Hovis , Alan Leslie , Phil Paone , David Siljenberg , Salvatore Storino , Gregory Uhlmann
发明人： William Hovis , Alan Leslie , Phil Paone , David Siljenberg , Salvatore Storino , Gregory Uhlmann
IPC分类号： G11C17/18
CPC分类号： G11C17/18
摘要： An eFuse reference cell on a chip provides a reference voltage that is greater than a maximum voltage produced by an eFuse cell having an unblown eFuse on the chip but less than a minimum voltage produced by an eFuse cell having a blown eFuse on the chip. A reference current flows through a resistor and an unblown eFuse in the eFuse reference cell, producing the reference voltage. The reference voltage is used to create a mirrored copy of the reference current in the eFuse cell. The mirrored copy of the reference current flows through an eFuse in the eFuse cell. A comparator receives the reference voltage and the voltage produced by the eFuse cell. The comparator produces an output logic level responsive to the voltage produced by the eFuse cell compared to the reference voltage.
摘要翻译：芯片上的eFuse参考单元提供的参考电压大于由芯片上具有未引脚eFuse的eFuse单元产生的最小电压，但小于由芯片上具有熔断eFuse的eFuse单元产生的最小电压。参考电流流过eFuse参考电池中的电阻和非吹出eFuse，产生参考电压。参考电压用于在eFuse单元中创建参考电流的镜像副本。参考电流的镜像副本通过eFuse单元中的eFuse流动。比较器接收参考电压和eFuse单元产生的电压。比较器产生一个响应于eFuse电池与参考电压相比产生的电压的输出逻辑电平。

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