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21. 发明授权

US08301840B2 Assigning cache priorities to virtual/logical processors and partitioning a cache according to such priorities 失效
标题翻译：将缓存优先级分配给虚拟/逻辑处理器，并根据这些优先级对高速缓存进行分区
公开(公告)号：US08301840B2
公开(公告)日：2012-10-30
申请号：US12637891
申请日：2009-12-15
申请人： Vaijayanthimala K. Anand , Diane G. Flemming , William A. Maron , Mysore S. Srinivas
发明人： Vaijayanthimala K. Anand , Diane G. Flemming , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/12
CPC分类号： G06F12/0895 , G06F9/5022 , G06F9/5077 , G06F12/126 , G06F2209/5021
摘要： Mechanisms are provided, for implementation in a data processing system having at least one physical processor and at least one associated cache memory, for allocating cache resources of the at least one cache memory to virtual processors of the data processing system. The mechanisms identify a plurality of high priority virtual processors in the data processing system. The mechanisms further determine a percentage of cache lines of the at least one cache memory to be assigned to high priority virtual processors. Moreover, the mechanisms mark a portion of the cache lines in the at least one cache memory as being evictable by only high priority virtual processors based on the determined percentage of cache lines to be assigned to high priority virtual processors. The marked portion of the cache lines cannot be evicted by lower priority virtual processors having a priority lower than the high priority virtual processors.
摘要翻译：提供了用于在具有至少一个物理处理器和至少一个相关联的高速缓冲存储器的数据处理系统中实现的机制，用于将至少一个高速缓冲存储器的高速缓存资源分配给数据处理系统的虚拟处理器。该机制识别数据处理系统中的多个高优先级虚拟处理器。这些机制进一步确定要分配给高优先级虚拟处理器的至少一个高速缓冲存储器的高速缓存行的百分比。此外，机制将所述至少一个高速缓冲存储器中的高速缓存行的一部分标记为仅基于所分配给高优先级虚拟处理器的高速缓存行的确定百分比仅被高优先级的虚拟处理器驱逐。高速缓存行的标记部分不能被优先级低于高优先级虚拟处理器的较低优先级的虚拟处理器驱逐。

22. 发明申请

US20120124299A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR EXTENDING A CACHE USING PROCESSOR REGISTERS 失效
标题翻译：使用处理器寄存器扩展缓存的系统，方法和计算机程序产品
公开(公告)号：US20120124299A1
公开(公告)日：2012-05-17
申请号：US12945354
申请日：2010-11-12
申请人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
发明人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
IPC分类号： G06F12/08
CPC分类号： G06F12/0895
摘要： According to one aspect of the present disclosure, a method and technique for using processor registers for extending a cache structure is disclosed. The method includes identifying a register of a processor, identifying a cache to extend, allocating the register as an extension of the cache, and setting an address of the register as corresponding to an address space in the cache.
摘要翻译：根据本公开的一个方面，公开了一种使用处理器寄存器来扩展高速缓存结构的方法和技术。该方法包括识别处理器的寄存器，识别要扩展的高速缓存，将该寄存器分配为高速缓存的扩展，以及将寄存器的地址设置为对应于高速缓存中的地址空间。

23. 发明授权

US08972706B2 Performance in predicting branches 有权
标题翻译：在预测分支中的表现
公开(公告)号：US08972706B2
公开(公告)日：2015-03-03
申请号：US13116515
申请日：2011-05-26
申请人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
发明人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/38
CPC分类号： G06F9/3844 , G06F9/38 , G06F9/3806 , G06F9/3848
摘要： A data processing system and computer program product for processing instructions. The instructions are processed by a processor unit while using a first table in a plurality of tables to predict a set of instructions needed by the processor unit after processing of a conditional instruction. An identification is formed that a rate of success in correctly predicting the set of instructions when using the first table is less than a threshold number. A sequence of the instructions being processed by the processor unit is searched for an instruction that matches a marker in a set of markers for identifying when to use the plurality of tables. An identification that the instruction that matches the marker is formed. A second table from the plurality of tables referenced by the marker is identified. The second table is used in place of the first table.
摘要翻译：用于处理指令的数据处理系统和计算机程序产品。所述指令由处理器单元处理，同时使用多个表中的第一表来预测在处理条件指令之后所述处理器单元所需的一组指令。形成识别，即当使用第一表时正确预测指令集的成功率小于阈值数。搜索由处理器单元处理的指令的序列，以搜索与用于识别何时使用多个表的一组标记中的标记相匹配的指令。形成与标记相符的指令的标识。识别由标记引用的多个表中的第二表。第二个表用于代替第一个表。

24. 发明授权

US08612986B2 Computer program product for scheduling ready threads in a multiprocessor computer based on an interrupt mask flag value associated with a thread and a current processor priority register value 失效
标题翻译：用于基于与线程相关联的中断屏蔽标志值和当前处理器优先级寄存器值在多处理器计算机中调度就绪线程的计算机程序产品
公开(公告)号：US08612986B2
公开(公告)日：2013-12-17
申请号：US13528645
申请日：2012-06-20
申请人： Jos M. Accapadi , Mathew Accapadi , Andrew Dunshea , Mark E. Hack , Agustin Mena, III , Mysore S. Srinivas
发明人： Jos M. Accapadi , Mathew Accapadi , Andrew Dunshea , Mark E. Hack , Agustin Mena, III , Mysore S. Srinivas
IPC分类号： G06F9/46 , G06F13/24
CPC分类号： G06F9/5027 , G06F9/4812
摘要： A computer program product for scheduling threads in a multiprocessor computer comprises computer program instructions configured to select a thread in a ready queue to be dispatched to a processor and determine whether an interrupt mask flag is set in a thread control block associated with the thread. If the interrupt mask flag is set in the thread control block associated with the thread, the computer program instructions are configured to select a processor, set a current processor priority register of the selected processor to least favored, and dispatch the thread from the ready queue to the selected processor.
摘要翻译：一种用于在多处理器计算机中调度线程的计算机程序产品包括计算机程序指令，其被配置为选择准备队列中的线程以分派到处理器，并且确定是否在与线程相关联的线程控制块中设置了中断屏蔽标志。如果在与线程相关联的线程控制块中设置了中断屏蔽标志，则将计算机程序指令配置为选择处理器，将所选处理器的当前处理器优先级寄存器设置为最不利，并将线程从就绪队列到所选择的处理器。

25. 发明授权

US08225327B2 Synchronizing access to a shared resource utilizing selective locking 有权
标题翻译：使用选择性锁定同步访问共享资源
公开(公告)号：US08225327B2
公开(公告)日：2012-07-17
申请号：US11227032
申请日：2005-09-15
申请人： David W. Mehaffy , Greg R. Mewhinney , Mysore S. Srinivas
发明人： David W. Mehaffy , Greg R. Mewhinney , Mysore S. Srinivas
IPC分类号： G06F9/46 , G06F9/45 , G06F17/00
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/544
摘要： A method and system for providing access to a shared resource utilizing selective locking are disclosed. According to one embodiment, a method is provided comprising receiving a request to perform a resource access operation on a shared resource, invoking a first routine to perform the resource access operation, detecting a data processing system exception generated in response to invoking the first routine, and invoking a second routine to perform the resource access operation in response to such detecting. In the described embodiment, the first routine comprises a dereference instruction to dereference a pointer to memory associated with the shared resource, the second routine comprises a lock acquisition instruction to acquire a global lock associated with the shared resource prior to a performance of the resource access operation and a lock release instruction to release the global lock once resource access operation has been performed.
摘要翻译：公开了一种利用选择性锁定来提供对共享资源的访问的方法和系统。根据一个实施例，提供了一种方法，包括接收对共享资源执行资源访问操作的请求，调用第一例程以执行资源访问操作，检测响应于调用第一例程而生成的数据处理系统异常，并且响应于这种检测，调用第二例程来执行资源访问操作。在所描述的实施例中，第一例程包括取消引用指令以取消对与共享资源相关联的存储器的指针的引用，第二例程包括在执行资源访问之前获取与共享资源相关联的全局锁定的锁获取指令一旦执行资源访问操作，操作和锁定释放指令释放全局锁定。

26. 发明申请

US20080256302A1 Programmable Data Prefetching 有权
标题翻译：可编程数据预取
公开(公告)号：US20080256302A1
公开(公告)日：2008-10-16
申请号：US11733352
申请日：2007-04-10
申请人： William A. Maron , Greg R. Mewhinney , Mysore S. Srinivas , David B. Whitworth
发明人： William A. Maron , Greg R. Mewhinney , Mysore S. Srinivas , David B. Whitworth
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A method, computer program product, and system are provided for prefetching data into a cache memory. As a program is executed an object identifier is obtained of a first object of the program. A lookup operation is performed on a data structure to determine if the object identifier is present in the data structure. Responsive to the object identifier being present in the data structure, a referenced object identifier is retrieved that is referenced by the object identifier. Then, the data associated with the referenced object identifier is prefetched from main memory into the cache memory.
摘要翻译：提供了一种用于将数据预取到高速缓冲存储器中的方法，计算机程序产品和系统。当执行程序时，获得程序的第一对象的对象标识符。对数据结构执行查找操作以确定对象标识符是否存在于数据结构中。响应于数据结构中存在的对象标识符，检索由对象标识符引用的引用对象标识符。然后，与被引用的对象标识符相关联的数据从主存储器预取到高速缓冲存储器中。

27. 发明授权

US09135080B2 Dynamically assigning a portion of physical computing resource to logical partitions based on characteristics of executing logical partitions 有权
标题翻译：基于执行逻辑分区的特性，将物理计算资源的一部分动态地分配给逻辑分区
公开(公告)号：US09135080B2
公开(公告)日：2015-09-15
申请号：US13460448
申请日：2012-04-30
申请人： Diane G. Flemming , Octavian F. Herescu , William A. Maron , Mysore S. Srinivas
发明人： Diane G. Flemming , Octavian F. Herescu , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F9/46 , G06F9/50 , G06F9/455
CPC分类号： G06F9/5011 , G06F9/45516 , G06F9/45558 , G06F9/4881 , G06F9/5088 , G06F2009/4557 , G06F2009/45579
摘要： A computer implemented method includes determining first characteristics of a first logical partition, the first characteristics including a memory footprint characteristic. The method includes assigning a first portion of a first set of physical computing resources to the first logical partition. The first set of physical computing resources includes a plurality of processors that includes a first processor having a first processor type and a second processor having a second processor type. The first portion includes the second processor. The method includes dispatching the first logical partition to execute using the first portion. The method includes creating a second logical partition that includes the second processor and assigning a second portion of the first set of physical computing resources to the second logical partition. The method includes dispatching the second logical partition to execute using the second portion.
摘要翻译：计算机实现的方法包括确定第一逻辑分区的第一特征，所述第一特征包括存储器占用特征。该方法包括将第一组物理计算资源的第一部分分配给第一逻辑分区。第一组物理计算资源包括多个处理器，其包括具有第一处理器类型的第一处理器和具有第二处理器类型的第二处理器。第一部分包括第二处理器。该方法包括使用第一部分调度第一逻辑分区以执行。该方法包括创建包括第二处理器并将第一组物理计算资源的第二部分分配给第二逻辑分区的第二逻辑分区。该方法包括使用第二部分调度第二逻辑分区以执行。

28. 发明授权

US08677050B2 System, method and computer program product for extending a cache using processor registers 失效
标题翻译：用于使用处理器寄存器扩展缓存的系统，方法和计算机程序产品
公开(公告)号：US08677050B2
公开(公告)日：2014-03-18
申请号：US12945354
申请日：2010-11-12
申请人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
发明人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
IPC分类号： G06F12/00
CPC分类号： G06F12/0895
摘要： According to one aspect of the present disclosure, a method and technique for using processor registers for extending a cache structure is disclosed. The method includes identifying a register of a processor, identifying a cache to extend, allocating the register as an extension of the cache, and setting an address of the register as corresponding to an address space in the cache.
摘要翻译：根据本公开的一个方面，公开了一种使用处理器寄存器来扩展高速缓存结构的方法和技术。该方法包括识别处理器的寄存器，识别要扩展的高速缓存，将该寄存器分配为高速缓存的扩展，以及将寄存器的地址设置为对应于高速缓存中的地址空间。

29. 发明申请

US20120304002A1 MANAGING ROLLBACK IN A TRANSACTIONAL MEMORY ENVIRONMENT 有权
标题翻译：管理在一个交易记忆环境中的滚动
公开(公告)号：US20120304002A1
公开(公告)日：2012-11-29
申请号：US13113663
申请日：2011-05-23
申请人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
发明人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
IPC分类号： G06F11/07
CPC分类号： G06F9/528 , G06F9/467
摘要： A system and technique for managing rollback in a transactional memory environment is disclosed. The system includes a processor, a transactional memory, and a transactional memory manager (TMM) configured to perform a rollback on the transactional memory. The TMM is configured to, responsive to detecting a begin transaction directive by the processor, detect an access of a first memory location of the transactional memory not needing rollback and indicate that the first memory location does not need to be rolled back while detecting an access to a second memory location of the transactional memory and indicating that a rollback will be required. The TMM is also configured to, responsive to detecting an end transaction directive after the begin transaction directive and a conflict requiring a rollback, omit a rollback of the first memory location while performing rollback on the second memory location.
摘要翻译：公开了一种用于在事务性存储器环境中管理回滚的系统和技术。该系统包括处理器，事务存储器和被配置为在事务存储器上执行回滚的事务性存储器管理器（TMM）。 TMM被配置为响应于检测到处理器的开始事务指令，检测不需要回滚的事务存储器的第一存储器位置的访问，并且指示在检测到访问期间不需要回滚第一存储器位置到事务存储器的第二存储器位置并且指示将需要回滚。 TMM还被配置为响应于在开始事务指令之后检测到结束事务指令和需要回滚的冲突，在第二存储器位置处执行回滚时，省略第一存储器位置的回滚。

30. 发明申请

US20120303591A1 MANAGING ROLLBACK IN A TRANSACTIONAL MEMORY ENVIRONMENT 有权
标题翻译：管理在一个交易记忆环境中的滚动
公开(公告)号：US20120303591A1
公开(公告)日：2012-11-29
申请号：US13451266
申请日：2012-04-19
申请人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
发明人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
IPC分类号： G06F17/30
CPC分类号： G06F9/528 , G06F9/467
摘要： According to one aspect of the present disclosure, a method and technique for managing rollback in a transactional memory environment is disclosed. The method includes, responsive to detecting a begin transaction directive by a processor supporting transactional memory processing, detecting an access of a first memory location not needing rollback and indicating that the first memory location does not need to be rolled back while detecting an access to a second memory location and indicating that a rollback will be required. The method also includes, responsive to detecting an end transaction directive after the begin transaction directive and a conflict requiring a rollback, omitting a rollback of the first memory location while performing rollback on the second memory location.
摘要翻译：根据本公开的一个方面，公开了一种用于在事务存储器环境中管理回滚的方法和技术。该方法包括：响应于由支持事务性存储器处理的处理器检测开始事务指令，检测不需要回滚的第一存储器位置的访问，并指示第一存储器位置不需要回滚，同时检测到对第二个内存位置，并指示需要回滚。该方法还包括：响应于在开始事务指令之后检测到结束事务指令和需要回滚的冲突，在第二存储器位置上执行回滚的同时省略第一存储器位置的回滚。

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