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21. 发明授权

US07502370B2 Network controller for obtaining a plurality of network port identifiers in response to load-store transactions from a corresponding plurality of operating system domains within a load-store architecture 有权
标题翻译：网络控制器，用于响应来自加载存储架构内的相应多个操作系统域的加载存储事务而获得多个网络端口标识符
公开(公告)号：US07502370B2
公开(公告)日：2009-03-10
申请号：US11045869
申请日：2005-01-27
申请人： Christopher J. Pettey
发明人： Christopher J. Pettey
IPC分类号： G06F13/10
CPC分类号： G06F3/00 , H04J3/12 , H04J3/16 , H04J3/22 , H04N5/50 , H04N21/443
摘要： A controller shareable by a plurality of operating system domains (OSDs) for communication on a network is disclosed. The controller includes a port for coupling to the network. The port transceives packets with the network for each of the plurality of OSDs. The controller also includes a plurality of replicated programming interfaces that each receive from a respective one of the plurality of OSDs a request to obtain a port ID for the port from the network. The controller obtains from the network a distinct port ID for each of the plurality of OSDs in response to the respective request. The request comprises one or more load-store transactions. In one embodiment, the controller is a shared Fiber Channel controller.
摘要翻译：公开了一种用于在网络上进行通信的多个操作系统域（OSD）共享的控制器。控制器包括用于耦合到网络的端口。该端口收发与多个OSD中的每一个的网络的分组。控制器还包括多个复制的编程接口，每个从多个OSD中的相应一个OSD接收从网络获得端口的端口ID的请求。响应于相应的请求，控制器从网络获得针对多个OSD中的每一个的不同端口ID。请求包括一个或多个加载存储事务。在一个实施例中，控制器是共享光纤通道控制器。

22. 发明授权

US07493416B2 Fibre channel controller shareable by a plurality of operating system domains within a load-store architecture 有权
标题翻译：光纤通道控制器可由加载存储架构内的多个操作系统域共享
公开(公告)号：US07493416B2
公开(公告)日：2009-02-17
申请号：US11046537
申请日：2005-01-27
申请人： Christopher J. Pettey
发明人： Christopher J. Pettey
IPC分类号： G06F15/16
CPC分类号： G06F13/12
摘要： A Fibre Channel controller shareable by a plurality of operating system domains (OSDs) is disclosed. The controller includes a programming interface, located within a system load-store memory map of each OSD by which the OSDs request the controller to perform I/O operations with remote FC devices. The programming interface includes a distinct control/status register (CSR) bank for each of OSD. The OSDs execute load-store instructions addressed to the programming interface to request the I/O operations. Selection logic selects as a target of each of the load-store transactions the distinct CSR bank for the OSD that executed the corresponding load-store instruction. An FC port obtains a distinct FC port identifier for each OSD and transceives FC frames with the remote FC devices using the distinct FC port identifier for each OSD in response to the I/O operation requests. In one embodiment, multiple blade servers share the controller via a shared I/O switch.
摘要翻译：公开了可由多个操作系统域（OSD）共享的光纤通道控制器。控制器包括位于每个OSD的系统加载存储存储器映射内的编程接口，OSD通过该接口请求控制器对远程FC设备执行I / O操作。编程接口包括用于每个OSD的不同的控制/状态寄存器（CSR）组。 OSD执行寻址到编程接口的加载存储指令以请求I / O操作。选择逻辑选择每个加载存储事务的对象，用于执行相应加载存储指令的OSD的不同CSR库。 FC端口为每个OSD获得不同的FC端口标识符，并且响应于I / O操作请求，使用针对每个OSD的不同FC端口标识符与远程FC设备收发FC帧。在一个实施例中，多个刀片服务器经由共享I / O开关共享控制器。

23. 发明授权

US6098134A Lock protocol for PCI bus using an additional "superlock" signal on the system bus 失效
标题翻译：使用系统总线上附加“超级锁”信号的PCI总线锁定协议
公开(公告)号：US6098134A
公开(公告)日：2000-08-01
申请号：US775130
申请日：1996-12-31
申请人： Peter Michels , Christopher J. Pettey , Thomas R. Seeman , Brian S. Hausauer
发明人： Peter Michels , Christopher J. Pettey , Thomas R. Seeman , Brian S. Hausauer
IPC分类号： G06F9/46 , G06F13/38 , G06F15/17
CPC分类号： G06F9/52
摘要： A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E)ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. According to a feature of the invention, provision is made for split transactions, i.e., a read request which is not satisfied while the processor requesting it is still on the bus, but instead the bus is relinquished and other transactions intervene before the read result is available. A contemporary microprocessor such as a P6 has a deferred transaction protocol to implement split transactions, but this protocol is not available on a PCI bus. Split transactions are done by a "retry" command on a PCI bus, wherein a read request that cannot be completed immediately is queued and a "retry" response is sent back to the requester on the bus; this instructs the requester to retry (send the same command again) at a later time. To avoid a situation where two processors issue locked cycles which are enqueued and retried in separate bridges, a "Superlock" signal is added to the processor bus, which is asserted by a bridge as soon as a locked transaction is enqueued, and thereafter neither bridge will accept a locked cycle issued by a processor, other than that locked read that was initiated by a processor and enqueued in the bridge and is being retried.
摘要翻译：计算机系统在微处理器本身的控制下具有处理器总线，并且该总线与主存储器通信，为大多数缓存填充操作提供高性能访问。此外，该系统包括一个或多个扩展总线，优选地在示例性实施例中为PCI类型。主机到PCI桥接器用于将处理器总线耦合到扩展总线。例如，其他总线可以通过PCI至（E）ISA网桥耦合到PCI总线。主机到PCI桥接器包含发布的写入和延迟读取请求的队列。所有交易排队通过桥梁，上游或下游。根据本发明的特征，提供分割事务，即，在请求它的处理器仍然在总线上时不满足的读请求，而是在读取结果为止之前放弃总线并且其他事务干预可用。诸如P6的当代微处理器具有延迟事务协议来实现分离事务，但是该协议在PCI总线上不可用。拆分事务通过PCI总线上的“重试”命令完成，其中立即不能完成的读取请求被排队，并且“重试”响应被发送回总线上的请求者; 这指示请求者稍后重试（再次发送相同的命令）。为了避免两个处理器发出锁定循环的情况，这些循环在单独的桥接器中排队并重试，“Superlock”信号被添加到处理器总线中，一旦锁定的事务被入队就由桥接器断言，然后两个桥接器将接受处理器发出的锁定循环，而不是由处理器启动并处于桥中并正在重试的锁定读取。

24. 发明授权

US09015350B2 Method and apparatus for a shared I/O network interface controller 有权
公开(公告)号：US09015350B2
公开(公告)日：2015-04-21
申请号：US13467143
申请日：2012-05-09
申请人： Christopher J. Pettey
发明人： Christopher J. Pettey
IPC分类号： G06F15/16 , G06F13/14 , H04L29/12 , H04L29/08 , H04L29/06
CPC分类号： H04L29/12009 , H04L29/0653 , H04L29/12018 , H04L45/74 , H04L61/10 , H04L67/1002 , H04L67/1017 , H04L67/1097 , H04L67/327 , H04L69/18 , H04L69/329
摘要： A shared network interface controller (NIC) interfaces a plurality of operating system domains as part of the load-store architecture of the operating system domains. A bus interface couples the NIC to a load-store domain bus (such as PCI-Express), using header information to associate data on the bus with an originating operating system domain. Transmit/receive logic connects the NIC to the network. Association logic allows the NIC to designate, and later lookup which destination MAC address (on the Ethernet side) is associated with which operating system domain. Descriptor register files and Control Status Registers (CSR's) specific to an operating system domain are duplicated and made available for each domain. Several direct memory access (DMA) engines are provided to improve throughput. Packet replication logic, filters (perfect and hash) and VLAN tables are used for looping back packets originating from one operating system domain to another and other operations.

25. 发明授权

US07587542B2 Device adapted to send information in accordance with a communication protocol 有权
标题翻译：适于根据通信协议发送信息的设备
公开(公告)号：US07587542B2
公开(公告)日：2009-09-08
申请号：US11193590
申请日：2005-07-28
申请人： Dwight Riley , Christopher J. Pettey
发明人： Dwight Riley , Christopher J. Pettey
IPC分类号： G06F13/36
CPC分类号： G06F13/4027 , G06F13/405
摘要： A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect (“RegPCI”) bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test (“POST”). Software configuration may also be determined upon detection of either an AGP or a RegPCI device connected to the common AGP/RegPCI bus.
摘要翻译：在可以配置为加速图形端口（“AGP”）总线与主机和存储器总线之间的桥接器的计算机系统中提供多用途核心逻辑芯片组，作为附加注册的外围组件互连（“ RegPCI“）总线和主机和内存总线，或作为主PCI总线和附加RegPCI总线之间的桥梁。多用途芯片组的功能是在计算机系统的制造时或在现场确定是否要实现AGP总线桥接器或附加的注册PCI总线桥接器。多用核心逻辑芯片组具有仲裁器，其具有针对在附加的已注册PCI总线上使用的每个PCI设备的请求（“REQ”）和Grant（“GNT”）信号线。可以通过硬件信号输入或在计算机系统配置或上电自检（“POST”）期间通过软件来选择多用途核心逻辑芯片组中的总线桥（AGP或RegPCI）类型。也可以在检测到连接到公共AGP / RegPCI总线的AGP或RegPCI设备时确定软件配置。

26. 发明授权

US07464207B2 Device operating according to a communication protocol 有权
标题翻译：设备根据通信协议进行操作
公开(公告)号：US07464207B2
公开(公告)日：2008-12-09
申请号：US11192561
申请日：2005-07-29
申请人： Dwight Riley , Christopher J. Pettey
发明人： Dwight Riley , Christopher J. Pettey
IPC分类号： G06F13/00
CPC分类号： G06F13/4027 , G06F13/405
摘要： A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect (“RegPCI”) bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test (“POST”). Software configuration may also be determined upon detection of either an AGP or a RegPCI device connected to the common AGP/RegPCI bus.
摘要翻译：在可以被配置为加速图形端口（“AGP”）总线与主机与存储器总线之间的桥接的计算机系统中提供了多用途核心逻辑芯片组，作为附加的注册的外围组件互连（“ RegPCI“）总线和主机和内存总线，或作为主PCI总线和附加RegPCI总线之间的桥梁。多用途芯片组的功能是在计算机系统的制造时或在现场确定是否要实现AGP总线桥接器或附加的注册PCI总线桥接器。多用核心逻辑芯片组具有仲裁器，其具有针对在附加的已注册PCI总线上使用的每个PCI设备的请求（“REQ”）和Grant（“GNT”）信号线。可以通过硬件信号输入或在计算机系统配置或上电自检（“POST”）期间通过软件来选择多用途核心逻辑芯片组中的总线桥（AGP或RegPCI）类型。也可以在检测到连接到公共AGP / RegPCI总线的AGP或RegPCI设备时确定软件配置。

27. 发明授权

US07149817B2 Infiniband TM work queue to TCP/IP translation 有权
标题翻译： Infiniband TM工作队列到TCP / IP转换
公开(公告)号：US07149817B2
公开(公告)日：2006-12-12
申请号：US09784761
申请日：2001-02-15
申请人： Christopher J. Pettey
发明人： Christopher J. Pettey
IPC分类号： G06F15/16 , G06F15/173 , G06F15/177 , G06F15/00 , G06F3/00
CPC分类号： H04L67/1097 , H04L29/06 , H04L69/16 , H04L69/161 , H04L69/162 , H04L69/163 , H04L69/168 , H04L69/169 , H04L69/329
摘要： A TCP-aware target adapter for accelerating TCP/IP connections between clients and servers, where the servers are interconnected over an Infiniband™ fabric and the clients are interconnected over a TCP/IP-based network. The TCP-aware target adapter includes an accelerated connection processor and a target channel adapter. The accelerated connection processor bridges TCP/IP transactions between the clients and the servers. The accelerated connection processor accelerates the TCP/IP connections prescribing Infiniband remote direct memory access operations to retrieve/provide transaction data from/to the servers. The target channel adapter is coupled to the accelerated connection processor. The target channel adapter supports Infiniband operations with the servers, including execution of the remote direct memory access operations to retrieve/provide the transaction data. The TCP/IP connections are accelerated by offloading TCP/IP processing otherwise performed by the servers to retrieve/provide said transaction data.
摘要翻译：用于加速客户端和服务器之间的TCP / IP连接的TCP感知目标适配器，其中服务器通过Infiniband（TM）架构互连，客户端通过基于TCP / IP的网络进行互连。 TCP感知目标适配器包括加速连接处理器和目标通道适配器。加速连接处理器在客户端和服务器之间桥接TCP / IP事务。加速连接处理器加速了TCP / IP连接，规定了Infiniband远程直接内存访问操作，以从服务器检索/提供事务数据。目标通道适配器耦合到加速连接处理器。目标通道适配器支持与服务器的Infiniband操作，包括执行远程直接内存访问操作以检索/提供事务数据。通过卸载TCP / IP处理来加速TCP / IP连接，否则由服务器执行以检索/提供所述事务数据。

28. 发明授权

US07099986B2 High speed peripheral interconnect apparatus, method and system 有权
公开(公告)号：US07099986B2
公开(公告)日：2006-08-29
申请号：US10945003
申请日：2004-09-20
申请人： Christopher J. Pettey , Dwight Riley
发明人： Christopher J. Pettey , Dwight Riley
IPC分类号： G06F13/38
CPC分类号： G06F13/4027 , G06F13/405
摘要： A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect (“RegPCI”) bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test (“POST”). Software configuration may also be determined upon detection of either an AGP or a RegPCI device connected to the common AGP/RegPCI bus.

29. 发明授权

US06266731B1 High speed peripheral interconnect apparatus, method and system 有权
标题翻译：高速外围互连设备，方法和系统
公开(公告)号：US06266731B1
公开(公告)日：2001-07-24
申请号：US09148042
申请日：1998-09-03
申请人： Dwight Riley , Christopher J. Pettey
发明人： Dwight Riley , Christopher J. Pettey
IPC分类号： G06F1338
CPC分类号： G06F13/105
摘要： A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued on the bus during the clock cycle immediately after the clock cycle when the initial command was issued. The extended commands and attributes utilize the standard pin connections of conventional PCI devices and buses making the present invention backward-compatible with existing (conventional) PCI devices and legacy computer systems. The conventional PCI command encoding is modified and the extended command is used to qualify the type of transaction and the attributes being used by the initiator of the transaction. The extended commands are divided into four groups based upon the transaction type and the extended command type. Transactions are either byte count or byte-enable transaction types. Extended command types are either validated or immediate. Some extended command encodings are reserved but can be assigned in the future to new extended commands that will behave predictable with current devices.
摘要翻译：为数字计算机系统上的外围组件提供高速连接装置，方法和系统。外围组件互连（PCI）规范用作扩展命令和属性集的基准。扩展命令和属性在发出初始命令的时钟周期之后的时钟周期内在总线上发出。扩展的命令和属性利用常规PCI设备和总线的标准引脚连接，使本发明与现有（常规）PCI设备和传统计算机系统向后兼容。传统的PCI命令编码被修改，扩展命令用于限定事务类型和事务发起者使用的属性。扩展命令根据事务类型和扩展命令类型分为四组。事务是字节计数或字节使能事务类型。扩展命令类型是验证的或立即的。一些扩展的命令编码被保留，但可以将来分配给新的扩展命令，这些扩展命令将使用当前设备来预测。

30. 发明授权

US06067590A Data bus agent including a storage medium between a data bus and the bus agent device 失效
标题翻译：数据总线代理，包括数据总线和总线代理设备之间的存储介质
公开(公告)号：US06067590A
公开(公告)日：2000-05-23
申请号：US873636
申请日：1997-06-12
申请人： Christopher J. Pettey , Dwight Riley
发明人： Christopher J. Pettey , Dwight Riley
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/405
摘要： A system and method of transferring data on a data bus is disclosed. The system includes a data bus agent having a storage medium connectable to a data bus and arranged to store data and a bus agent device adapted to receive data from the storage medium. The method includes driving a signal on a data bus by a first bus agent, sampling the signal at a second bus agent, storing the sampled signal in a storage medium associated with the second bus agent, and processing the stored signal at the second bus agent.
摘要翻译：公开了一种在数据总线上传送数据的系统和方法。该系统包括具有可连接到数据总线并被布置成存储数据的存储介质和适于从存储介质接收数据的总线代理设备的数据总线代理。该方法包括通过第一总线代理在数据总线上驱动信号，在第二总线代理处采样信号，将采样信号存储在与第二总线代理相关联的存储介质中，以及在第二总线代理处理存储的信号。

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