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21. 发明授权

US07746607B2 Substrate triggering for ESD protection in SOI 有权
标题翻译： SOI中ESD保护的衬底触发
公开(公告)号：US07746607B2
公开(公告)日：2010-06-29
申请号：US11380525
申请日：2006-04-27
申请人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H02H3/22
CPC分类号： H01L27/0266
摘要： Electrostatic discharge (ESD) protection device and process for protecting a conventional FET. The device includes at least one FET body forming a resistance, and a triggering circuit coupled to a protection FET and the resistance. The resistance raises a voltage of the at least one body, such that the protection FET is triggered at a voltage lower than the conventional FET.
摘要翻译：静电放电（ESD）保护装置和保护常规FET的工艺。该器件包括至少一个形成电阻的FET体，以及耦合到保护FET和电阻的触发电路。电阻提高至少一个体的电压，使得保护FET在比常规FET低的电压下被触发。

22. 发明授权

US07457086B2 High voltage ESD power clamp 有权
标题翻译：高压ESD电源钳
公开(公告)号：US07457086B2
公开(公告)日：2008-11-25
申请号：US11614659
申请日：2006-12-21
申请人： Kiran V. Chatty , Robert J. Gauthier, Jr. , Mahmoud A. Mousa , Mujahid Muhammad , Christopher S. Putnam
发明人： Kiran V. Chatty , Robert J. Gauthier, Jr. , Mahmoud A. Mousa , Mujahid Muhammad , Christopher S. Putnam
IPC分类号： H02H3/20 , H02H3/22 , H02H9/04
CPC分类号： H01L27/0266 , H03K17/08142
摘要： Method and device for protecting against electrostatic discharge. The method includes configuring a gate of at least one upper transistor of a transistor network connected between power rails to be biased to a prescribed value, and coupling an electrostatic discharge event to a gate of a lower transistor of the transistor network. The at least one upper and at least one lower transistors of the transistor network are respectively coupled between the power rails from a higher voltage to a lower voltage.
摘要翻译：用于防止静电放电的方法和装置。该方法包括配置连接在电源轨之间的晶体管网络的至少一个上晶体管的栅极以被偏置到规定值，以及将静电放电事件耦合到晶体管网络的下晶体管的栅极。晶体管网络的至少一个上部和至少一个下部晶体管分别从较高电压到较低电压耦合在电源轨之间。

23. 发明授权

US07397641B2 Apparatus and method for improved triggering and oscillation suppression of ESD clamping devices 失效
标题翻译：用于改善ESD钳位装置的触发和振荡抑制的装置和方法
公开(公告)号：US07397641B2
公开(公告)日：2008-07-08
申请号：US11276411
申请日：2006-02-28
申请人： Albert M. Chu , Robert J. Gauthier, Jr. , Junjun Li , Thomas W. Wyckoff
发明人： Albert M. Chu , Robert J. Gauthier, Jr. , Junjun Li , Thomas W. Wyckoff
IPC分类号： H02H9/00 , H02H1/00
CPC分类号： H01L27/0266
摘要： An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) includes an RC trigger device configured between a pair of power rails, a first control path coupled to the RC trigger device, and a second control path coupled to the RC trigger device. A power clamp is configured between the power rails for discharging current from an ESD event, the power clamp having an input coupled to outputs of the first and second control paths, the power clamp independently controllable by the first and second control paths. The first and second control paths are further configured to prevent the power clamp from reactivating following an initial deactivation of the power clamp.
摘要翻译：用于保护集成电路免受静电放电（ESD）的装置包括RC触发装置，其配置在耦合到RC触发装置的一对电源轨，第一控制路径和耦合到RC触发装置的第二控制路径之间。功率钳被配置在用于从ESD事件放电的电源轨之间，功率钳具有耦合到第一和第二控制路径的输出的输入，功率钳由第一和第二控制路径独立地控制。第一和第二控制路径还被配置为防止在电源钳的初始去激活之后电源钳位被重新激活。

24. 发明授权

US07253066B2 MOSFET with decoupled halo before extension 失效
标题翻译：扩展前分离光环的MOSFET
公开(公告)号：US07253066B2
公开(公告)日：2007-08-07
申请号：US10785895
申请日：2004-02-24
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthier, Jr. , Carl J. Radens , William R. Tonti
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthier, Jr. , Carl J. Radens , William R. Tonti
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L21/28114 , H01L29/42376 , H01L29/66553 , H01L29/6659
摘要： An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are intended to alter the series resistance of the device. Formation of the inverse-T structure can be made by a damascene method in which a temporary layer deposited over the layer that will form the cross bar of the T has an aperture formed in it to hold the gate electrode, the aperture being lined with vertical sidewalls that provide space for the ledges that form the T. Another method of gate electrode formation starts with a layer of poly, forms a block for the gate electrode, covers the horizontal surfaces outside the gate with an etch-resistant material and etches horizontally to remove material above the cross bars on the T, the cross bars being protected by the etch resistant material.
摘要翻译：反向T晶体管通过使晕轮注入，深S / D注入和延伸注入分离的方法形成，使得阈值电压可以通过调整晕轮植入来设定，而不受扩展植入物的变化的影响旨在改变装置的串联电阻。逆T结构的形成可以通过镶嵌方法来形成，其中沉积在层上的临时层将形成T的横杆，其中形成有形成在其中的孔以保持栅电极，孔径垂直排列为形成T的壁架提供空间的侧壁。栅电极形成的另一种方法从多层开始，形成用于栅电极的块，用耐蚀刻材料覆盖栅极外的水平表面，并水平蚀刻去除T上的横杆上方的材料，横杆由耐蚀刻材料保护。

25. 发明授权

US07085113B2 ESD protection power clamp for suppressing ESD events occurring on power supply terminals 失效
标题翻译： ESD保护电源钳位，用于抑制电源端子发生的ESD事件
公开(公告)号：US07085113B2
公开(公告)日：2006-08-01
申请号：US10711085
申请日：2004-08-20
申请人： Robert J. Gauthier, Jr. , Junjun Li
发明人： Robert J. Gauthier, Jr. , Junjun Li
IPC分类号： H02H9/00 , H02H3/22
CPC分类号： H01L27/0266
摘要： An ESD protection power clamp for suppressing ESD events. A clamping transistor having power source connections connected across the power supply terminals of an integrated circuit is connected to clamp the voltage during an ESD event. An RC timing circuit defines a time interval where ESD voltage for triggering the FET out of conduction. An inverter circuit connects the RC and timing circuit to the clamping FET. A dynamic feedback transistor is connected in series with one stage of the inverter and the power supply. During an ESD event, the feedback transistor delays the time for disabling the FET transistor, providing increased immunity against mistriggering of the clamping transistor, and forces the circuit to reset following the mistrigger event.
摘要翻译：用于抑制ESD事件的ESD保护电源钳。具有连接在集成电路的电源端子上的电源连接的钳位晶体管被连接以在ESD事件期间钳位电压。 RC定时电路定义用于触发FET导通的ESD电压的时间间隔。逆变器电路将RC和定时电路连接到钳位FET。动态反馈晶体管与逆变器和电源的一级串联连接。在ESD事件期间，反馈晶体管延迟了禁止FET晶体管的时间，提供了抵抗钳位晶体管失谐的增强的抗扰性，并迫使电路在雾触发器事件之后复位。

26. 发明授权

US06965503B2 Electro-static discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US06965503B2
公开(公告)日：2005-11-15
申请号：US10605441
申请日：2003-09-30
申请人： John Connor , Robert J. Gauthier, Jr. , Christopher S. Putnam , Alan L. Roberts
发明人： John Connor , Robert J. Gauthier, Jr. , Christopher S. Putnam , Alan L. Roberts
IPC分类号： H01L27/02 , H02H9/00
CPC分类号： H01L27/0285
摘要： An ESD protection circuit including the following: one or more inverters (I1, I2, I3), each of the one or more inverters having an input and an output; an RC network (11) having an output node (RCT), output node (RCT) connected with the input of at least one of said one or more inverters; a clamping device (N3) joined with the output of at least one of one or more inverters (I1, I2, I3); and a feedback device (NKP) in communication with clamping device (N3) and output node (RCT) of RC network (11). An RC network may include one or more resistors, and one or more decoupling capacitors. In one embodiment, feedback device (NKP) is an NFET and each of one or more inverters (I1, I2, I3) includes a PFET and NFET pair (P0/N0, P1/N1, P2/N2).
摘要翻译：一种ESD保护电路，包括：一个或多个反相器（I 1，I 2，I 3），一个或多个反相器中的每一个具有输入和输出; 具有输出节点（RCT）的RC网络（11），与所述一个或多个逆变器中的至少一个的输入端连接的输出节点（RCT）与一个或多个逆变器（I 1，I 2，I 3）中的至少一个的输出端连接的夹持装置（N 3）; 以及与RC网络（11）的钳位装置（N 3）和输出节点（RCT）通信的反馈装置（NKP）。 RC网络可以包括一个或多个电阻器和一个或多个去耦电容器。在一个实施例中，反馈装置（NKP）是NFET，并且一个或多个反相器（I 1，I 2，I 3）中的每一个包括PFET和NFET对（P 0 / N 0，P 1 / N 1，P 2 / N 2）。

27. 发明授权

US06476445B1 Method and structures for dual depth oxygen layers in silicon-on-insulator processes 有权
公开(公告)号：US06476445B1
公开(公告)日：2002-11-05
申请号：US09303277
申请日：1999-04-30
申请人： Jeffrey Scott Brown , Andres Bryant , Robert J. Gauthier, Jr. , Randy William Mann , Steven Howard Voldman
发明人： Jeffrey Scott Brown , Andres Bryant , Robert J. Gauthier, Jr. , Randy William Mann , Steven Howard Voldman
IPC分类号： H01L2701
CPC分类号： H01L27/1203 , H01L21/26533 , H01L21/76232 , H01L21/76264 , H01L21/76267 , H01L21/76283
摘要： A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.

28. 发明授权

US06352905B1 Method and structure of high and low K buried oxide for SOI technology 失效
标题翻译：用于SOI技术的高K和低K埋氧体的方法和结构
公开(公告)号：US06352905B1
公开(公告)日：2002-03-05
申请号：US09702787
申请日：2000-11-01
申请人： Robert J. Gauthier, Jr. , Dominic J. Schepis , Steven H. Voldman
发明人： Robert J. Gauthier, Jr. , Dominic J. Schepis , Steven H. Voldman
IPC分类号： H01L2176
CPC分类号： H01L21/7624
摘要： A method and structure for forming an integrated circuit wafer comprises forming a substrate having first and second portions, depositing a first insulator over the substrate, patterning the first insulator such that the first insulator remains only over the first portion, depositing a second insulator over substrate (the first insulator has different thermal dissipation characteristics than the second insulator), polishing the second insulator to form a planar surface, and attaching a silicon film over the first insulator and the second insulator.
摘要翻译：用于形成集成电路晶片的方法和结构包括形成具有第一和第二部分的衬底，在衬底上沉积第一绝缘体，图案化第一绝缘体，使得第一绝缘体仅保留在第一部分之上，在衬底上沉积第二绝缘体（第一绝缘体具有与第二绝缘体不同的散热特性），抛光第二绝缘体以形成平坦表面，并且在第一绝缘体和第二绝缘体上附着硅膜。

29. 发明授权

US06232639B1 Method and structure to reduce latch-up using edge implants 失效
标题翻译：使用边缘植入物减少闭锁的方法和结构
公开(公告)号：US06232639B1
公开(公告)日：2001-05-15
申请号：US09107900
申请日：1998-06-30
申请人： Faye D. Baker , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven J. Holmes , Robert K. Leidy , Edward J. Nowak , Steven H. Voldman
发明人： Faye D. Baker , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven J. Holmes , Robert K. Leidy , Edward J. Nowak , Steven H. Voldman
IPC分类号： H01L2976
CPC分类号： H01L21/823878 , H01L27/0921 , Y10S148/137
摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.
摘要翻译：本发明的优选实施例克服了现有技术的限制，并且提供了一种通过在阱边缘处形成植入物来增加CMOS器件的闩锁抗扰度的装置和方法。优选的方法使用混合抗蚀剂在N阱和/或P阱的边缘形成这些植入物。植入物减少了寄生晶体管中少数载流子的寿命，从而降低了寄生晶体管的增益。这降低了CMOS器件闭锁的倾向。优选实施例方法允许形成这些植入物，而不需要比现有技术方法更多的掩蔽步骤。此外，用于形成植入物的优选方法导致与孔的边缘自对准的植入物。

30. 发明授权

US06187617B1 Semiconductor structure having heterogeneous silicide regions and method for forming same 失效
标题翻译：具有异质硅化物区域的半导体结构及其形成方法
公开(公告)号：US06187617B1
公开(公告)日：2001-02-13
申请号：US09363558
申请日：1999-07-29
申请人： Robert J. Gauthier, Jr. , Randy W. Mann , Steven H. Voldman
发明人： Robert J. Gauthier, Jr. , Randy W. Mann , Steven H. Voldman
IPC分类号： H01L21336
CPC分类号： H01L29/4933 , H01L21/28052 , H01L21/28518 , H01L21/28568 , H01L21/823418 , H01L21/823443 , H01L29/456
摘要： A process for forming heterogeneous silicide structures on a semiconductor substrate (10) includes implanting molybdenum ions into selective areas of the semiconductor substrate (10) to form molybdenum regions (73, 74, 75, 76). Titanium is then deposited over the semiconductor substrate (10). The semiconductor substrate (10) is annealed at a temperature between approximately 600° C. and approximately 700° C. During the annealing process, the titanium deposited in areas outside the molybdenum regions (73, 74, 75, 76) interacts with silicon on the substrate to form titanium silicide in a high resistivity C49 crystal phase. The titanium deposited in areas within the molybdenum regions (73, 74, 75, 76) interacts with silicon to form titanium silicide in a low resistivity C54 crystal phase because the presence of molybdenum ions in silicon lowers the energy barrier for crystal phase transformation between the C49 phase and the C54 phase.
摘要翻译：在半导体衬底（10）上形成异质硅化物结构的方法包括将钼离子注入到半导体衬底（10）的选择区域中以形成钼区（73,74,75,76）。然后将钛沉积在半导体衬底（10）上。半导体衬底（10）在大约600℃和大约700℃之间的温度下退火。在退火过程中，沉积在钼区域（73,74,75,76）之外的区域中的钛与硅该基板在高电阻率C49晶相中形成硅化钛。在钼区域（73,74,75,76）中的区域中沉积的钛与硅相互作用以在低电阻率C54晶体相中形成硅化钛，因为硅中的钼离子的存在降低了能量势垒以进行晶体相变 C49相和C54相。

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