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21. 发明授权

US08185862B2 Architectural level power-aware optimization and risk mitigation 失效
标题翻译：建筑级电力感知优化和风险减轻
公开(公告)号：US08185862B2
公开(公告)日：2012-05-22
申请号：US12835640
申请日：2010-07-13
申请人： Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
发明人： Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks to implement one or more instructions; determining an instruction execution sequence based on the code profile and reassigning the instruction sequence to spread operation to different blocks on the IC to reduce hot spots; and synthesizing the generated processor chip specification into a computer readable description of the custom integrated circuit for semiconductor fabrication.
摘要翻译：公开了通过接收包括计算机可读代码的定制集成电路的规范并生成计算机可读代码的简档以确定指令使用来自动合成定制集成电路的系统和方法; 自动生成针对所述计算机可读代码独特定制的处理器架构，所述处理器架构具有一个或多个处理块以实现一个或多个指令; 基于代码简档确定指令执行序列，并重新分配指令序列以将操作扩展到IC上的不同块以减少热点; 并将生成的处理器芯片规范合成到用于半导体制造的定制集成电路的计算机可读描述中。

22. 发明申请

US20120017189A1 ARCHITECTURAL LEVEL POWER-AWARE OPTIMIZATION AND RISK MITIGATION 失效
标题翻译：建筑水平力量优化和风险缓解
公开(公告)号：US20120017189A1
公开(公告)日：2012-01-19
申请号：US12835640
申请日：2010-07-13
申请人： Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
发明人： Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
IPC分类号： G06F17/50 , G06F9/44
CPC分类号： G06F17/5068 , G06F17/5045
摘要： Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks to implement one or more instructions; determining an instruction execution sequence based on the code profile and reassigning the instruction sequence to spread operation to different blocks on the IC to reduce hot spots; and synthesizing the generated processor chip specification into a computer readable description of the custom integrated circuit for semiconductor fabrication.
摘要翻译：公开了通过接收包括计算机可读代码的定制集成电路的规范并生成计算机可读代码的简档以确定指令使用来自动合成定制集成电路的系统和方法; 自动生成针对所述计算机可读代码独特定制的处理器架构，所述处理器架构具有一个或多个处理块以实现一个或多个指令; 基于代码简档确定指令执行序列，并重新分配指令序列以将操作扩展到IC上的不同块以减少热点; 并将生成的处理器芯片规范合成到用于半导体制造的定制集成电路的计算机可读描述中。

23. 发明申请

US20090230746A1 VEHICLE SEAT AND A DISC RECLINER THEREFOR 有权
标题翻译：车辆座椅及其碟机
公开(公告)号：US20090230746A1
公开(公告)日：2009-09-17
申请号：US11909355
申请日：2006-04-06
申请人： Pius Ng , Randolph Villarroel
发明人： Pius Ng , Randolph Villarroel
IPC分类号： B60N2/235
CPC分类号： B60N2/20 , B60N2/236 , B60N2205/50
摘要： A vehicle seat has a seat back and a seat cushion and a pair of recliners hingedly mounting the seat back to the seat cushion providing pivotal movement of a seat back relative to a seat cushion. Each of the recliners has a guide plate configured to be mounted to the seat cushion and a toothed plate rotatably assembled to the guide plate. The toothed disc has a flange having a series of internal teeth thereon. A plurality of pawls is mounted between the toothed plate and the guide plate. The pawls each has a toothed surface and is moveable between a locked position with the toothed surfaces engaging the series of teeth to lock the toothed plate relative to the guide plate, and an unlocked position with the toothed surfaces spaced from the teeth of the guide plate to allow movement of the toothed plate relative to the guide plate. A plurality of guides extends from the guide plate, guiding the pawls between the locked and unlocked positions. A cam is rotatably mounted between the guide plate and the toothed plate. The cam has a cam surface defined by a plurality of lobes for selective engagement with the pawls, selectively moving the pawls between the locked and unlocked positions. A spring continuously biases the cam, urging the pawls toward the locked position. A bushing is secured to the cam. The cam and the bushing have a lost motion connection therebetween. A rod extending through the bushing on each of the recliners to gang the recliners together for simultaneous operation. The guide plate and the toothed plate have abutments that limit relative rotational travel therebetween.
摘要翻译：车辆座椅具有座椅靠背和座垫，并且一对躺椅铰接地将座椅靠背安装到座垫上，提供座椅靠背相对于座垫的枢转运动。每个倾斜器具有构造成安装到座垫的引导板和可旋转地组装到引导板的齿板。齿盘具有在其上具有一系列内齿的凸缘。多个棘爪安装在齿板和引导板之间。棘爪各自具有齿形表面，并且可在锁定位置与啮合该系列齿的齿表面之间移动，以相对于引导板锁定齿形板，以及解锁位置，其中齿形表面与引导板的齿间隔开以允许齿形板相对于导板移动。多个引导件从引导板延伸，在锁定位置和解锁位置之间引导棘爪。凸轮可旋转地安装在导向板和带齿板之间。凸轮具有由多个凸角限定的凸轮表面，用于与棘爪选择性地接合，选择性地将棘爪移动在锁定位置和解锁位置之间。弹簧连续地偏压凸轮，将棘爪推向锁定位置。衬套固定在凸轮上。凸轮和衬套之间具有迷失的运动连接。在每个倾斜板上延伸穿过套管的杆，以将倾斜器组合在一起用于同时操作。引导板和齿板具有限制其间的相对旋转行程的基台。

24. 发明授权

US06761408B2 Linear recliner having an internal cam spring 失效
公开(公告)号：US06761408B2
公开(公告)日：2004-07-13
申请号：US10277480
申请日：2002-10-22
申请人： Kung M. Lim , Pius Ng
发明人： Kung M. Lim , Pius Ng
IPC分类号： B60N222
CPC分类号： B60N2/224
摘要： A linear recliner for a vehicle seat assembly providing selectively lockable pivotal adjustment of a seat back pivotally coupled to a seat cushion between a plurality of reclined seating positions. A housing is fixedly secured to the seat cushion. The housing includes a bore extending between front and rear ends of the housing. A chamber is formed within the housing adjacent and open to a portion of the bore. A rod extends between one end pivotally coupled to the seat back and an opposite end slidably carried within the bore of the housing for axial displacement of the rod within the bore during pivotal movement of the seat back. The rod includes a rack of teeth extending towards the chamber. A pawl lockably engagable with the rack of teeth in the rod for preventing axial displacement of the rod within the bore is pivotally coupled to the housing for movement in and out of the locking engagement with the rack of teeth in the rod. The pawl includes an opening extending between opposing and spaced apart upper and lower edges. A step portion and a relief portion define the lower edge. A cam having a primary lobe engagable with the step portion of the lower edge and a secondary lobe engagable with the upper edge is pivotally coupled to the housing for moving the primary and secondary lobes in and out of camming engagement with the step portion and upper edge, respectively. While engaged with the step portion, the primary lobe of the cam maintains the pawl lockably engaged with the rack of teeth in the rod. During manual rotation of the cam, the secondary lobe engages the upper edge to move the pawl out of locking engagement with the rack of teeth in the rod when the primary lobe disengages the step portion and extends towards the relief portion. An internal spring extends between one end fixedly secured to the pawl and an opposite end fixedly secured to the cam. The internal spring simultaneously and continuously biases the pawl towards locking engagement with the rack of teeth in the rod and the primary lobe of the cam towards camming engagement with the step portion.

25. 发明授权

US06275891B1 Modular and scalable system for signal and multimedia processing 有权
标题翻译：用于信号和多媒体处理的模块化和可扩展的系统
公开(公告)号：US06275891B1
公开(公告)日：2001-08-14
申请号：US09257840
申请日：1999-02-25
申请人： Tuan Q Dao , Pius Ng , Paul Look
发明人： Tuan Q Dao , Pius Ng , Paul Look
IPC分类号： G96F1300
CPC分类号： G09G5/39 , G06F15/8007 , G09G2330/021 , G09G2340/02 , G09G2360/125 , H04N19/42 , H04N19/61
摘要： A modular, scalable system architecture that includes a data traffic master for providing high-bandwidth, shared memory connections to two or more processor units. The system architecture includes an array of memory modules coupled to an array of processor units by a traffic master. Each of the memory modules is connected to the traffic master by a data channel, and each data channel includes an address path and a data path. The data channels all share a common data path bit-width. On the other hand, the processor units are each coupled to the traffic master by data busses that have address and data path widths dictated by their design. Although the address path width of a given processor unit may be unable to span the address space of the shared memory, the processor unit can nonetheless access any memory location through the use of page pointers. Further, although the data path width of a given processor unit may be too large for a single data channel to support, several data channels may be combined to provide the required data path width. The traffic master includes a processor interface port for each processor unit, and a router. The processor interface ports convert data bus address and write data signals into corresponding data channel address and write data signals, and also convert data channel read data signals into corresponding data bus read data signals. The router routes the data channel signals between the processor interface ports and the memory modules. When applied to multimedia systems with a microcontroller, one or more digital signal processors, and one or more hardware accelerators, this architecture is expected to provide a substantial increase in processing capabilities.
摘要翻译：模块化，可扩展的系统架构，其包括用于向两个或多个处理器单元提供高带宽共享存储器连接的数据流量主机。系统架构包括由业务主控器耦合到处理器单元阵列的存储器模块阵列。每个存储器模块通过数据通道连接到业务主控器，并且每个数据通道包括地址路径和数据路径。数据通道都共享一个公共数据路径位宽。另一方面，处理器单元各自通过具有由其设计规定的地址和数据路径宽度的数据总线耦合到业务主控。虽然给定处理器单元的地址路径宽度可能不能跨越共享存储器的地址空间，但是处理器单元仍然可以通过使用页指针访问任何存储器位置。此外，尽管给定的处理器单元的数据路径宽度可能对于单个数据信道来说可能太大，但可以组合几个数据信道以提供所需的数据路径宽度。流量主控器包括用于每个处理器单元的处理器接口端口和路由器。处理器接口端口将数据总线地址和数据信号转换成相应的数据通道地址和写数据信号，并将数据通道读数据信号转换为相应的数据总线读数据信号。路由器在处理器接口端口和存储器模块之间路由数据信道信号。当应用于具有微控制器，一个或多个数字信号处理器和一个或多个硬件加速器的多媒体系统时，预期这种架构将大大增加处理能力。

26. 发明授权

US08572544B2 Programmatic auto-convergent method for “physical layout power hot-spot” risk aware ASIP architecture customization for performance optimization 失效
标题翻译：用于“物理布局电源热点”的风险识别ASIP架构定制的程序化自动收敛方法进行性能优化
公开(公告)号：US08572544B2
公开(公告)日：2013-10-29
申请号：US13452893
申请日：2012-04-22
申请人： Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
发明人： Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5068 , G06F17/5045
摘要： Systems and methods are disclosed to automatically method to manage power in a custom integrated circuit (IC) design with a code profile by receiving an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operations or activities over a plurality of processing blocks to reduce hot spots; applying sub-region weight distributions to estimate power hot-spot locations; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
摘要翻译：公开了系统和方法以通过基于代码简档接收指令执行序列并重新分配或延迟指令序列来扩展多个操作或活动来自动地通过代码简档来管理定制集成电路（IC）设计中的电力的方法的加工块来减少热点; 应用子区域权重分布来估计功率热点位置; 以及将生成的架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

27. 发明申请

US20130111426A1 PROGRAMMATIC AUTO-CONVERGENT METHOD FOR PHYSICAL DESIGN FLOORPLAN AWARE RE-TARGETABLE TOOL SUITE GENERATION (COMPILER-IN-THE-LOOP) FOR SIMULTANEOUS INSTRUCTION LEVEL (SOFTWARE) POWER OPTIMIZATION AND ARCHITECTURE LEVEL PERFORMANCE OPTIMIZATION FOR ASIP DESIGN 失效
标题翻译：用于物理设计FLOORPLAN的可编程自动变换方法用于同步指令级（软件）的功率优化和架构级别性能优化用于ASIP设计的可重定向工具套件生成（编译器）
公开(公告)号：US20130111426A1
公开(公告)日：2013-05-02
申请号：US13452891
申请日：2012-04-22
申请人： Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
发明人： Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： Systems and methods are disclosed to automatically synthesize a custom integrated circuit by automatically generating an application specific instruction set processor architecture uniquely customized to the computer readable code with a compiler-in-the-loop to compile, assemble and link code for each processor architecture iteration, the processor architecture having one or more processing blocks on the IC executing one or more instructions; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
摘要翻译：系统和方法被公开以通过自动地生成针对每个处理器架构迭代来编译，组合和链接代码的编译器在循环中独特地定制到计算机可读代码的应用特定指令集处理器架构来自动合成定制集成电路所述处理器架构在所述IC上具有执行一个或多个指令的一个或多个处理块; 以及将生成的架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

28. 发明申请

US20130104097A1 PROGRAMMATIC AUTO-CONVERGENT METHOD FOR "PHYSICAL LAYOUT POWER HOT-SPOT" RISK AWARE ASIP ARCHITECTURE CUSTOMIZATION FOR PERFORMANCE OPTIMIZATION 失效
标题翻译： “物理布局功率热点”的编程自动变换方法风险评估ASIP架构自定义性能优化
公开(公告)号：US20130104097A1
公开(公告)日：2013-04-25
申请号：US13452893
申请日：2012-04-22
申请人： Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
发明人： Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： Systems and methods are disclosed to automatically method to manage power in a custom integrated circuit (IC) design with a code profile by receiving an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operations or activities over a plurality of processing blocks to reduce hot spots; applying sub-region weight distributions to estimate power hot-spot locations; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
摘要翻译：公开了系统和方法以通过基于代码简档接收指令执行序列并重新分配或延迟指令序列来扩展多个操作或活动来自动地通过代码简档来管理定制集成电路（IC）设计中的电力的方法的加工块来减少热点; 应用子区域权重分布来估计功率热点位置; 以及将生成的架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

29. 发明申请

US20120185809A1 ARCHITECTURE OPTIMIZER 失效
标题翻译：架构优化器
公开(公告)号：US20120185809A1
公开(公告)日：2012-07-19
申请号：US13008900
申请日：2011-01-19
申请人： Suresh Kadiyala , Pius Ng , Anand Pandurangam , Satish Padmanabhan , James Player
发明人： Suresh Kadiyala , Pius Ng , Anand Pandurangam , Satish Padmanabhan , James Player
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) described by a computer readable code or model. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters of the architecture in a hierarchical manner until all timing and hardware constraints expressed as a cost function are met using an architecture optimizer (AO); and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
摘要翻译：公开了系统和方法以自动生成由计算机可读代码或模型描述的定制集成电路（IC）。 IC具有一个或多个时序和硬件限制。该系统从静态简档和计算机可读代码的动态简档中提取定义处理器架构的参数; 通过以层次的方式改变架构的一个或多个参数来迭代地优化处理器架构，直到使用架构优化器（AO）满足表示为成本函数的所有定时和硬件约束; 并将生成的处理器架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

30. 发明申请

US20120096417A1 INTEGRATED DATA MODEL BASED FRAMEWORK FOR DRIVING DESIGN CONVERGENCE FROM ARCHITECTURE OPTIMIZATION TO PHYSICAL DESIGN CLOSURE 失效
标题翻译：基于数据模型的集成框架，用于从建筑优化到物理设计关闭的设计合并
公开(公告)号：US20120096417A1
公开(公告)日：2012-04-19
申请号：US12906785
申请日：2010-10-18
申请人： Ananth Durbha , Pius Ng , Satish Padmanabhan
发明人： Ananth Durbha , Pius Ng , Satish Padmanabhan
IPC分类号： G06F17/50 , G06F9/455 , G06F9/45
CPC分类号： G06F17/5045 , G06F2217/06 , G06F2217/86
摘要： Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; encoding architecture level knowledge in a data model to generate and pass new constraints for physical synthesis of a chip specification uniquely customized to the computer readable code; receiving a look-ahead cost function during architecture optimization consistent with cost observed later in the flow after detailed physical synthesis is performed, wherein the look-ahead cost function is generated from a prior iteration and supplied to a subsequent iteration through the data model; automatically translating information available at one optimization point into a constraint for another optimization point invoked at a different place in the design flow using the data model; and synthesizing a computer readable description of the chip specification into the custom integrated circuit for semiconductor fabrication.
摘要翻译：公开了系统和方法，通过接收包括计算机可读代码和定制集成电路上的一个或多个约束的定制集成电路的规范来自动地合成定制集成电路; 编码数据模型中的架构级知识，以生成和传递新的约束，用于物理合成芯片规范，该芯片规范独特地定制到计算机可读代码; 在进行详细的物理合成之后，在结构优化期间接收与之前的流程中观察到的成本一致的先行成本函数，其中，先行成本函数是从先前的迭代生成的并提供给通过数据模型的后续迭代; 将在一个优化点处可用的信息自动翻译成使用数据模型在设计流程中不同位置调用的另一优化点的约束; 以及将芯片规格的计算机可读描述合成到用于半导体制造的定制集成电路中。

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