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21. 发明授权

US06812122B2 Method for forming a voltage programming element 有权
标题翻译：用于形成电压编程元件的方法
公开(公告)号：US06812122B2
公开(公告)日：2004-11-02
申请号：US10095889
申请日：2002-03-12
申请人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , Max G. Levy , Rick L. Mohler , William R. Tonti , Wayne M. Trickle
发明人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , Max G. Levy , Rick L. Mohler , William R. Tonti , Wayne M. Trickle
IPC分类号： H01L2144
CPC分类号： H01L21/763 , H01L23/5252 , H01L27/10861 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： Method for forming a first one time, voltage programmable logic element in a semiconductor substrate of first conductivity type, forming a first layer beneath a surface of the substrate, the first layer having a second conductivity type. A trench is formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench.
摘要翻译：用于形成第一导电类型的半导体衬底中的第一次电压可编程逻辑元件的方法，在所述衬底的表面下方形成第一层，所述第一层具有第二导电类型。沟槽通过表面形成并穿过第一层。沟槽包括内表面，衬在内表面的电介质材料和填充衬里沟槽的导电材料。第一逻辑元件被配置为使得施加在导电材料和第一层之间的预定电压或更高的电压导致沟槽区域内的击穿。

22. 发明授权

US06753590B2 High impedance antifuse 有权
公开(公告)号：US06753590B2
公开(公告)日：2004-06-22
申请号：US10064375
申请日：2002-07-08
申请人： John A. Fifield , Russell J. Houghton , William R. Tonti
发明人： John A. Fifield , Russell J. Houghton , William R. Tonti
IPC分类号： H01L2900
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , Y10S438/957 , H01L2924/00
摘要： A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the substrate and said electrode of said second device, said second insulator having a second value of said given characteristic that is different from said first value. The electrodes of the diode and the FET are coupled to one another, and a source of programming energy is coupled to the diode to cause it to permanently decrease in resistivity when programmed. The programmed state of the diode is indicated by a current in the FET, which is read by a sense latch. Thus a small resistance change in the diode translates to a large signal gain/change in the latch. This allows the diode to be programmed at lower voltages.

23. 发明授权

US06346846B1 Methods and apparatus for blowing and sensing antifuses 失效
标题翻译：用于吹制和检测反熔丝的方法和装置
公开(公告)号：US06346846B1
公开(公告)日：2002-02-12
申请号：US09466479
申请日：1999-12-17
申请人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , William R. Tonti , Nicholas M. Van Heel
发明人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , William R. Tonti , Nicholas M. Van Heel
IPC分类号： H01H3776
CPC分类号： G11C5/145 , G11C17/18
摘要： Methods and apparatus for blowing and sensing antifuses are provided. Specifically, in a first aspect, a method is provided for changing the state of one of a plurality of antifuses by selecting one of the bank of antifuses and applying a high voltage to change the state of the selected antifuse. In second and third aspects, apparatus are provided for performing the method of the first aspect. In a fourth aspect, a method is provided for boosting a voltage that includes the steps of generating a first voltage within a first stage storage mechanism of a first stage voltage booster circuit, generating a second voltage equaling about twice the first voltage within a first and a second, second stage storage mechanism of a second stage voltage booster circuit, and generating about thrice the first voltage based on the second voltage of the second stage voltage booster circuit. In a fifth aspect, apparatus are provided for performing the method of the fourth aspect.
摘要翻译：提供了用于吹制和检测反熔丝的方法和装置。具体地，在第一方面中，提供一种通过选择一组反熔丝中的一个并且施加高电压来改变所选择的反熔丝的状态来改变多个反熔丝之一的状态的方法。在第二和第三方面中，提供了用于执行第一方面的方法的装置。在第四方面，提供了一种用于升压电压的方法，包括以下步骤：在第一级升压电路的第一级存储机构内产生第一电压，产生等于第一级升压电路中第一电压的大约两倍的第二电压，第二级升压电路的第二级第二级存储机构，并且基于第二级升压电路的第二电压产生约三倍的第一电压。在第五方面中，提供了用于执行第四方面的方法的装置。

24. 发明授权

US06281731B1 Control of hysteresis characteristic within a CMOS differential receiver 有权
标题翻译：控制CMOS差分接收器内的滞后特性
公开(公告)号：US06281731B1
公开(公告)日：2001-08-28
申请号：US09428639
申请日：1999-10-27
申请人： John A. Fifield , Russell J. Houghton , Wilbur D. Pricer , William R. Tonti
发明人： John A. Fifield , Russell J. Houghton , Wilbur D. Pricer , William R. Tonti
IPC分类号： H03K3297
CPC分类号： H03K3/3565 , H03K3/02337
摘要： A differential receiver has a switching point accurately set according to a reference voltage, which switching point is dynamically modified, that is, dc hysteresis is provided, by a circuit internal to the differential receiver. Positioning of the resultant hysteresis characteristic about the reference signal is adjusted by establishing a backgate voltage differential between an input transistor and a reference transistor of the differential receiver. A switching circuit is also provided for controlling switching of a hysteresis circuit at the reference signal plus or minus a desired offset. The switching circuit is gated by an output signal of the input transistor.
摘要翻译：差分接收器具有根据参考电压精确设置的开关点，通过差分接收器内部的电路动态地修改切换点，即提供直流滞后。通过在差分接收器的输入晶体管和参考晶体管之间建立背栅电压差来调整所产生的关于参考信号的滞后特性的定位。还提供了一种开关电路，用于控制滞后电路在参考信号加或减所需偏移的切换。开关电路由输入晶体管的输出信号选通。

25. 发明授权

US06195027B1 Capacitive precharging and discharging network for converting N bit input into M bit output 失效
标题翻译：用于将N位输入转换为M位输出的电容式预充放电网络
公开(公告)号：US06195027B1
公开(公告)日：2001-02-27
申请号：US09302744
申请日：1999-04-30
申请人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Christopher P. Miller , Steven W. Tomashot , William R. Tonti
发明人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Christopher P. Miller , Steven W. Tomashot , William R. Tonti
IPC分类号： H03M720
CPC分类号： G11C8/10
摘要： A method and structure for decoding n input signals and their complements to one of m output signals is provided. A capacitive network is provided having m output nodes. The output nodes are precharged to a given voltage value. N input signals and their complements are provided each having either a high value or a low value. At least one but less than all of the output nodes are discharged to a value less than the given voltage but greater than ground in output patterns responsive to given input patterns of the true and complement values of the input signals. The output patterns of the discharged nodes is such as to provide one and only one discharged or one and only one undischarged node for any given pattern of input signals. Preferably the capacitive network includes NMOS inversion capacitors.
摘要翻译：提供了用于将n个输入信号及其与m个输出信号之一的补码进行解码的方法和结构。提供具有m个输出节点的电容网络。输出节点预充电到给定的电压值。提供N个输入信号及其补码，每个具有高值或低值。响应于输入信号的真值和补码值的给定输入模式，至少一个但不到所有输出节点的输出模式被放电到小于给定电压但大于输出模式的输出值的值。放电节点的输出模式是为任何给定模式的输入信号提供一个且仅一个放电或一个且仅一个未充电节点。优选地，电容网络包括NMOS反转电容器。

26. 发明授权

US6121106A Method for forming an integrated trench capacitor 失效
标题翻译：用于形成集成沟槽电容器的方法
公开(公告)号：US6121106A
公开(公告)日：2000-09-19
申请号：US38395
申请日：1998-03-11
申请人： Wayne F. Ellis , Russell J. Houghton , Max G. Levy , William R. Tonti
发明人： Wayne F. Ellis , Russell J. Houghton , Max G. Levy , William R. Tonti
IPC分类号： H01L21/334 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/10894 , H01L29/66181
摘要： A shallow trench capacitor is disclosed that is fabricated by forming a shallow trench in a substrate extending below a surface of the substrate. A dielectric layer having a preselected thickness is grown in the shallow trench, and a polysilicon layer is deposited over the dielectric layer. The polysilicon layer is then planarized down to the nitride or pad layer forming a capacitor. By utilizing a non-critical mask to open up selected regions, isolation structures may then be formed through shallow trench technology.
摘要翻译：公开了一种浅沟槽电容器，其通过在衬底的表面下方延伸的衬底中形成浅沟槽来制造。在浅沟槽中生长具有预选厚度的电介质层，并且在电介质层上沉积多晶硅层。然后将多晶硅层平坦化成形成电容器的氮化物或焊盘层。通过利用非关键掩模来打开所选择的区域，然后可以通过浅沟槽技术形成隔离结构。

27. 发明授权

US5761114A Multi-level storage gain cell with stepline 失效
标题翻译：带梯级的多级存储增益单元
公开(公告)号：US5761114A
公开(公告)日：1998-06-02
申请号：US803034
申请日：1997-02-19
申请人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Christopher P. Miller , William R. Tonti
发明人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Christopher P. Miller , William R. Tonti
IPC分类号： G11C11/56
CPC分类号： G11C11/565 , G11C16/30
摘要： A method and apparatus for using multi-level signals in a gain cell is shown. The method involves of first, storing a value of a multi-level signal in the gain cell. A stepping waveform is then applied to the gain cell and the gain cell outputs a conduction signal when the level of the stepping waveform corresponds to the value of the multilevel signal that is stored within the gain cell. Finally, the value of the multi-level signal is determined through the conduction signal and the corresponding level of the stepping waveform. The gain cell includes an input device, a storage device and a level comparator, which responds to the stepping waveform generated from a stepping signal generator and outputs the conduction signal for determining the value of the multi-level signal stored in the storage device.
摘要翻译：示出了在增益单元中使用多电平信号的方法和装置。该方法首先在增益单元中存储多电平信号的值。然后，当增益单元的步进波形对应于存储在增益单元内的多电平信号的值时，增益单元输出导通信号。最后，通过导通信号和步进波形的相应电平来确定多电平信号的值。增益单元包括响应于从步进信号发生器产生的步进波形的输入装置，存储装置和电平比较器，并输出用于确定存储在存储装置中的多电平信号的值的导通信号。

28. 发明授权

US06347058B1 Sense amplifier with overdrive and regulated bitline voltage 有权
标题翻译：具有过驱动和稳压位线电压的感应放大器
公开(公告)号：US06347058B1
公开(公告)日：2002-02-12
申请号：US09574806
申请日：2000-05-19
申请人： Russell J. Houghton , Christopher P. Miller
发明人： Russell J. Houghton , Christopher P. Miller
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C7/06 , G11C11/4091 , G11C11/4094
摘要： In many DRAM (Dynamic Random Access Memory) architectures, a sense amplifier detects and amplifies a small voltage differential between complementary bitline pairs to read from/write to a DRAM memory cell. The access speed of the DRAM is dependent on the speed of the transition, due to this amplification, of the bitline pairs from an equalized, pre-charged voltage level to final (within a given sensing cycle) high and low levels. The transition speed of the bitline pairs can be increased by providing a higher overdrive voltage to the sense amplifier. As DRAM technologies are scaled successively smaller, the overdrive voltage must be controlled to avoid compromising the reliability of the DRAM. Accordingly, the present invention relates to a DRAM circuit which provides a transiently higher overdrive voltage only during sensing. The overdrive is provided by a pre-charged capacitive source utilizing the circuit's natural capacitance. The pre-charged capacitive source and the high-going bitline are coupled to a common node during sensing. The amount of capacitance and the level of pre-charge voltage are determined so as to arrive at a target voltage on the common node. The target voltage may be adjusted so as to achieve the correct write-back voltage for the high-going bitline.
摘要翻译：在许多DRAM（动态随机存取存储器）结构中，读出放大器检测并放大互补位线对之间的小的电压差，以从DRAM存储单元读/写。 DRAM的存取速度取决于由均衡的预充电电压电平到最终（在给定的感测周期内）高电平和低电平的位线对的转换速度。可以通过向感测放大器提供更高的过驱动电压来增加位线对的转换速度。随着DRAM技术的缩小，必须控制过驱动电压，以避免损害DRAM的可靠性。因此，本发明涉及仅在感测期间提供瞬时更高的过驱动电压的DRAM电路。利用电路的自然电容，预充电电容源提供过驱动。在感测期间，预充电电容源和高速位线耦合到公共节点。确定电容量和预充电电压的水平以便达到公共节点上的目标电压。可以调整目标电压以便为高速位线获得正确的回写电压。

29. 发明授权

US4413191A Array word line driver system 失效
标题翻译：阵列字线驱动系统
公开(公告)号：US4413191A
公开(公告)日：1983-11-01
申请号：US260576
申请日：1981-05-05
申请人： Russell J. Houghton
发明人： Russell J. Houghton
IPC分类号： G11C11/414 , G11C11/413 , G11C11/415 , H01L21/8229 , H01L27/102 , H03K17/04 , H03K17/16 , H03K17/62
CPC分类号： G11C11/415
摘要： This invention provides a system for selectively driving one word line of a plurality of word lines in a memory array which includes a first highly capacitive common line connected to a plurality of driver circuits, each of which has connected to its output a respective word line and each of which includes a transistor having a capacitive junction connected to the common line. Means are provided for charging the common line and for rapidly discharging the common line through a selected driver circuit to its associated word line. Additionally, a second highly capacitive common line is connected to a point of reference potential through a resistor, with each of the driver circuits being connected between said first and second common lines.
摘要翻译：本发明提供了一种用于选择性地驱动存储器阵列中的多个字线的一条字线的系统，该系列包括连接到多个驱动器电路的第一高容性公共线，每个驱动电路已连接到其输出相应的字线，每个都包括具有连接到公共线的电容结的晶体管。提供了用于对公共线充电并且用于通过所选择的驱动器电路将公共线快速放电到其相关联的字线的装置。此外，第二高电容公共线通过电阻器连接到参考电位点，其中每个驱动电路连接在所述第一和第二公共线之间。

30. 发明授权

US06876250B2 Low-power band-gap reference and temperature sensor circuit 有权
标题翻译：低功率带隙参考和温度传感器电路
公开(公告)号：US06876250B2
公开(公告)日：2005-04-05
申请号：US10345039
申请日：2003-01-15
申请人： Louis L. Hsu , Rajiv V. Joshi , Russell J. Houghton
发明人： Louis L. Hsu , Rajiv V. Joshi , Russell J. Houghton
IPC分类号： G01K7/01 , G05F3/30 , H01L23/34 , G05F1/10
CPC分类号： G05F3/30 , G01K7/015 , H01L23/34 , H01L2924/0002 , H01L2924/00
摘要： A combined low-voltage, low-power band-gap reference and temperature sensor circuit is provided for providing a band-gap reference parameter and for sensing the temperature of a chip, such as an eDRAM memory unit or CPU chip, using the band-gap reference parameter. The combined sensor circuit is insensitive to supply voltage and a variation in the chip temperature. The power consumption of both circuits, i.e., the band-gap reference and the temperature sensor circuits, encompassing the combined sensor circuit is less than one μW. The combined sensor circuit can be used to monitor local or global chip temperature. The result can be used to (1) regulate DRAM array refresh cycle time, e.g., the higher the temperature, the shorter the refresh cycle time, (2) to activate an on-chip or off-chip cooling or heating device to regulate the chip temperature, (3) to adjust internally generated voltage level, and (4) to adjust the CPU (or microprocessor) clock rate, i.e., frequency, so that the chip will not overheat. The combined band-gap reference and temperature sensor circuit of the present invention can be implemented within battery-operated devices having at least one memory unit. The low-power circuits of the sensor circuit extend battery lifetime and data retention time of the cells of the at least one memory unit.
摘要翻译：提供了组合的低压，低功率带隙参考和温度传感器电路，用于提供带隙参考参数，并且用于使用频带参考参数来感测诸如eDRAM存储器单元或CPU芯片的芯片的温度，间隙参考参数。组合的传感器电路对电源电压和芯片温度的变化不敏感。包含组合传感器电路的两个电路（即带隙基准和温度传感器电路）的功耗小于1μW。组合传感器电路可用于监测局部或全局芯片温度。结果可用于（1）调节DRAM阵列刷新周期时间，例如温度越高，刷新周期时间越短，（2）启动片上或片外冷却或加热装置来调节芯片温度，（3）调节内部产生的电压电平，（4）调整CPU（或微处理器）的时钟频率，即频率，使芯片不会过热。本发明的组合带隙参考和温度传感器电路可以在具有至少一个存储器单元的电池供电的装置内实现。传感器电路的低功率电路延长了至少一个存储器单元的单元的电池寿命和数据保持时间。

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