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21. 发明申请

US20120213023A1 SYSTEMS AND METHODS FOR MEMORY DEVICE PRECHARGING 有权
标题翻译：用于存储器件预处理的系统和方法
公开(公告)号：US20120213023A1
公开(公告)日：2012-08-23
申请号：US13030341
申请日：2011-02-18
申请人： James W. Dawson , Rajiv V. Joshi , Noam Jungmann , Elazar Kachir , Rouwaida N. Kanj , Ehud Nir , Donald W. Plass
发明人： James W. Dawson , Rajiv V. Joshi , Noam Jungmann , Elazar Kachir , Rouwaida N. Kanj , Ehud Nir , Donald W. Plass
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C7/1048 , G11C11/413
摘要： Systems and methods for determining optimal memory device precharge voltages are provided herein. In addition, systems and methods for providing localized sense amplification and circuit assist circuitry are described herein. Embodiments provide for determining precharge multipliers that may be used to determine the optimal precharge voltage based on a precharge source voltage. According to embodiments, the precharge source voltage may be Vdd or Vcs. Optimizing the precharge voltage maximizes memory device performance and functional characteristics, including, but not limited to, stability, efficiency, power, writability, and reliability.
摘要翻译：本文提供了确定最佳存储器件预充电电压的系统和方法。此外，本文描述了用于提供局部感测放大和电路辅助电路的系统和方法。实施例提供了用于确定预充电乘法器，其可以用于基于预充电源电压来确定最佳预充电电压。根据实施例，预充电源电压可以是Vdd或Vcs。优化预充电电压使存储器件性能和功能特性最大化，包括但不限于稳定性，效率，功率，写入性和可靠性。

22. 发明申请

US20110225438A1 COMPUTER PROGRAM PRODUCT FOR CONTROLLING A STORAGE DEVICE HAVING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES 有权
标题翻译：用于控制具有各元件选择电源电压的存储设备的计算机程序产品
公开(公告)号：US20110225438A1
公开(公告)日：2011-09-15
申请号：US13115149
申请日：2011-05-25
申请人： Rajiv V. Joshi , Jente B. Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B. Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G06F1/32
CPC分类号： G11C11/417 , G11C5/14
摘要： A computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：用于使用每元件可选择的电源电压来控制存储设备的计算机程序产品在保持特定性能水平的同时在存储设备中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

23. 发明申请

US20100313070A1 BROKEN-SPHERES METHODOLOGY FOR IMPROVED FAILURE PROBABILITY ANALYSIS IN MULTI-FAIL REGIONS 有权
标题翻译：改进的多故障区域故障概率分析方法
公开(公告)号：US20100313070A1
公开(公告)日：2010-12-09
申请号：US12477361
申请日：2009-06-03
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Zhuo Li , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Zhuo Li , Sani R. Nassif
IPC分类号： G06F11/26
CPC分类号： G06F11/008
摘要： A failure probability for a system having multi-fail regions is computed by generating failure directions in a space whose dimensions are the system parameters under consideration. The failure directions are preferably uniform, forming radial slices. The failure directions may be weighted. The radial slices have fail boundaries defining fail regions comparable to broken shells. The distribution of the system parameters is integrated across the broken shell regions to derive a failure contribution for each failure direction. The failure probability is the sum of products of each failure contribution and its weight. Failure contributions are computed using equivalent expressions dependent on the number of dimensions, which can be used to build lookup tables for normalized fail boundary radii. The entire process can be iteratively repeated with successively increasing failure directions until the failure probability converges. The method is particularly useful in analyzing failure probability of electrical circuits such as memory cells.
摘要翻译：通过在尺寸为所考虑的系统参数的空间中生成故障方向来计算具有多故障区域的系统的故障概率。故障方向优选均匀，形成径向切片。失败方向可能被加权。径向切片的失效边界定义与断裂壳相当的失效区域。系统参数的分布在破裂的外壳区域中集成，以导出每个故障方向的故障贡献。故障概率是每个失效贡献的乘积和其重量之和。使用等同表达式计算故障贡献，取决于维数，可用于构建归一化失效边界半径的查找表。可以连续增加故障方向，迭代重复整个过程，直到故障概率收敛。该方法在分析诸如存储器单元之类的电路的故障概率方面特别有用。

24. 发明申请

US20090129193A1 ENERGY EFFICIENT STORAGE DEVICE USING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES 失效
标题翻译：使用全能选择电源电压的能源效率存储设备
公开(公告)号：US20090129193A1
公开(公告)日：2009-05-21
申请号：US11941168
申请日：2007-11-16
申请人： Rajiv V. Joshi , Jente B. Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B. Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G11C5/14 , G06F12/00
CPC分类号： G11C11/417 , G11C5/14
摘要： An energy efficient storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：使用每元件可选择的电源电压的节能存储装置在保持特定的性能水平的同时在存储装置中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

25. 发明申请

US20080195325A1 SYSTEM AND COMPUTER PROGRAM FOR EFFICIENT CELL FAILURE RATE ESTIMATION IN CELL ARRAYS 审中-公开
标题翻译：系统和计算机程序在细胞阵列中有效的细胞失败率估计
公开(公告)号：US20080195325A1
公开(公告)日：2008-08-14
申请号：US12103804
申请日：2008-04-16
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
IPC分类号： G01N33/00
CPC分类号： G06F17/5036 , G11C29/028 , G11C29/54 , G11C29/56004 , G11C29/56008 , G11C2029/0403
摘要： A system and computer program for efficient cell failure rate estimation in cell arrays provides an efficient mechanism for raising the performance of memory arrays beyond present levels/yields. An initial search is performed across cell circuit parameters to determine failures with respect to a set of performance variables. For a single failure region the initial search can be a uniform sampling of the parameter space and when enough failure points have been accumulated, a mean is chosen from the mean of the detected failure points. Mixture importance sampling (MIS) is then performed to efficiently estimate the single failure region. For multiple failure regions, a particular failure region is selected by varying the memory circuit cell parameters along a random set of vectors until failures are detected, thus identifying the boundary of the failure region of interest as the closest failure region. A new mean is chosen for MIS in conformity with the location of the detected boundary.
摘要翻译：用于在单元阵列中有效的单元故障率估计的系统和计算机程序为提高存储器阵列的性能提供了超出当前水平/产量的有效机制。在单元电路参数之间执行初始搜索以确定关于一组性能变量的故障。对于单个故障区域，初始搜索可以是参数空间的均匀采样，并且当已经累积了足够的故障点时，从检测到的故障点的平均值中选择一个平均值。然后执行混合重要性采样（MIS）以有效地估计单个故障区域。对于多个故障区域，通过沿随机矢量集改变存储器电路单元参数直到检测到故障来选择特定故障区域，从而将感兴趣的故障区域的边界识别为最接近的故障区域。根据检测到的边界的位置，为MIS选择新的平均值。

26. 发明授权

US07380225B2 Method and computer program for efficient cell failure rate estimation in cell arrays 有权
标题翻译：用于单元阵列中有效单元故障率估计的方法和计算机程序
公开(公告)号：US07380225B2
公开(公告)日：2008-05-27
申请号：US11375477
申请日：2006-03-14
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G11C29/028 , G11C29/54 , G11C29/56004 , G11C29/56008 , G11C2029/0403
摘要： A method and computer program for efficient cell failure rate estimation in cell arrays provides an efficient mechanism for raising the performance of memory arrays beyond present levels/yields. An initial search is performed across cell circuit parameters to determine failures with respect to a set of performance variables. For a single failure region the initial search can be a uniform sampling of the parameter space and when enough failure points have been accumulated, a mean is chosen from the mean of the detected failure points. Mixture importance sampling (MIS) is then performed to efficiently estimate the single failure region. For multiple failure regions, a particular failure region is selected by varying the memory circuit cell parameters along a random set of vectors until failures are detected, thus identifying the boundary of the failure region of interest as the closest failure region. A new mean is chosen for MIS in conformity with the location of the detected boundary.
摘要翻译：用于在单元阵列中有效的单元故障率估计的方法和计算机程序提供了一种有效的机制，用于提高存储器阵列的性能超过现有水平/产量。在单元电路参数之间执行初始搜索以确定关于一组性能变量的故障。对于单个故障区域，初始搜索可以是参数空间的均匀采样，并且当已经累积了足够的故障点时，从检测到的故障点的平均值中选择一个平均值。然后执行混合重要性采样（MIS）以有效地估计单个故障区域。对于多个故障区域，通过沿随机矢量集改变存储器电路单元参数直到检测到故障来选择特定故障区域，从而将感兴趣的故障区域的边界识别为最接近的故障区域。根据检测到的边界的位置，为MIS选择新的平均值。

27. 发明授权

US09471732B2 Equivalent device statistical modeling for bitline leakage modeling 有权
公开(公告)号：US09471732B2
公开(公告)日：2016-10-18
申请号：US13616991
申请日：2012-09-14
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Mechanisms are provided for modeling a plurality of devices of an integrated circuit design as a single statistically equivalent wide device. An integrated circuit design is analyzed to identify a portion of the integrated circuit design having the plurality of devices. For the plurality of devices, a statistical model of a single statistically equivalent wide device is generated which has a statistical distribution of at least one operating characteristic of the single statistically equivalent wide device that captures statistical operating characteristic distributions of individual devices in the plurality of devices. At least one statistical operating characteristic of the single statistically equivalent wide device is a complex non-linear function of the statistical operating characteristics of the individual devices. The integrated circuit design is modeled using the single statistically equivalent wide device.

28. 发明授权

US08799732B2 Methodology for correlated memory fail estimations 有权
标题翻译：相关内存失败估算方法
公开(公告)号：US08799732B2
公开(公告)日：2014-08-05
申请号：US13369633
申请日：2012-02-09
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
IPC分类号： G11C29/00 , G06F11/00 , G11C29/08 , G06F17/18
CPC分类号： G11C29/08 , G06F17/18 , G11C29/56008
摘要： Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area.
摘要翻译：通过基于多个参数构建用于分组的存储器单元模型来估计具有不同存储单元组的存储器阵列的相关故障分布，使用快速统计分析建立存储器单元模型的故障条件，计算每个存储器的参数的失效边界基于其相应的故障条件的单元模型，构建以失败边界为特征的存储器阵列模型。使用分配给存储器单元和外围逻辑元件的参数的随机值来重复模拟存储器阵列模型的操作，以识别每个模拟操作的存储器单元故障。对于每个存储器阵列模型计算平均值和方差，然后可以通过选择表现出最佳均值和方差的分组来识别最佳架构，受任何其他电路要求（例如功率或面积）的限制。

29. 发明授权

US08588009B2 Circuit for memory cell recovery 失效
标题翻译：用于记忆细胞恢复的电路
公开(公告)号：US08588009B2
公开(公告)日：2013-11-19
申请号：US13247362
申请日：2011-09-28
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Jente B. Kuang , Carl J. Radens
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Jente B. Kuang , Carl J. Radens
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/02 , G11C7/04 , G11C11/417 , G11C11/419
摘要： An apparatus and method for combating the effects of bias temperature instability (BTI) in a memory cell. Bit lines connecting to a memory cell contain two alternate paths criss-crossing to connect a lower portion of a first bit line to an upper portion of a second bit line, and to connect a lower portion of the second bit line to an upper portion of the first bit line. Alternative to activating transistors on the bit lines to read and write to the memory cell, transistors on the alternative paths may be activated to read and write to the memory cell from the opposite bit lines. The memory cell may be read through the bit lines to a sense amplifier, the transistors on the bit lines are subsequently deactivated and the transistors on the alternate paths are activated to write transposed bit values to the memory cell, thereby reversing the biases.
摘要翻译：一种用于抵抗存储单元中偏置温度不稳定性（BTI）的影响的装置和方法。连接到存储器单元的位线包含两个交替的交替路径，以将第一位线的下部连接到第二位线的上部，并且将第二位线的下部连接到第二位线的上部第一个位线。在位线上激活晶体管以读取和写入存储器单元的替代方案是替代路径上的晶体管可被激活以从相对的位线读取和写入存储器单元。存储器单元可以通过位线读取到读出放大器，位线上的晶体管随后被去激活，并且激活交替路径上的晶体管以将转置的位值写入存储器单元，从而反转偏置。

30. 发明申请

US20130212444A1 METHODOLOGY FOR CORRELATED MEMORY FAIL ESTIMATIONS 有权
标题翻译：相关记忆失败估算方法
公开(公告)号：US20130212444A1
公开(公告)日：2013-08-15
申请号：US13369633
申请日：2012-02-09
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
IPC分类号： G11C29/08 , G06F11/26
CPC分类号： G11C29/08 , G06F17/18 , G11C29/56008
摘要： Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area.
摘要翻译：通过基于多个参数构建用于分组的存储器单元模型来估计具有不同存储单元组的存储器阵列的相关故障分布，使用快速统计分析建立存储器单元模型的故障条件，计算每个存储器的参数的失效边界基于其相应的故障条件的单元模型，构建以失败边界为特征的存储器阵列模型。使用分配给存储器单元和外围逻辑元件的参数的随机值来重复模拟存储器阵列模型的操作，以识别每个模拟操作的存储器单元故障。对于每个存储器阵列模型计算平均值和方差，然后可以通过选择表现出最佳均值和方差的分组来识别最佳架构，受任何其他电路要求（例如功率或面积）的限制。

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