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21. 发明授权

US08904115B2 Cache with multiple access pipelines 有权
标题翻译：具有多路访问管道的缓存
公开(公告)号：US08904115B2
公开(公告)日：2014-12-02
申请号：US13212895
申请日：2011-08-18
申请人： Abhijeet Ashok Chachad , Raguram Damodaran , Jonathan (Son) Hung Tran , Timothy David Anderson , Sanjive Agarwala
发明人： Abhijeet Ashok Chachad , Raguram Damodaran , Jonathan (Son) Hung Tran , Timothy David Anderson , Sanjive Agarwala
IPC分类号： G06F12/00 , G06F7/483 , G06F12/02 , G06F1/32 , G06F9/30 , H03M13/35 , H03M13/29 , G06F11/10 , H03K19/00 , H03K21/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.
摘要翻译：并行流水线用于访问共享内存。通过处理器通过第一管线访问共享存储器以从共享存储器访问缓存的数据。通过存储器访问单元通过第二管线访问共享存储器以访问共享存储器。维持第一组标签以供第一管线使用以控制对高速缓冲存储器的访问，而第二组标签被维护供第二管道用于访问共享存储器。在每个流水线检查其相应的一组标签之后，执行仲裁以访问第一流水线中的事务请求的高速缓冲存储器和第二流水线中的事务请求。

22. 发明授权

US08532247B2 Integer and half clock step division digital variable clock divider 有权
标题翻译：整数和半时钟分频数字可变时钟分频器
公开(公告)号：US08532247B2
公开(公告)日：2013-09-10
申请号：US13247265
申请日：2011-09-28
申请人： Ramakrishnan Venkatasubramanian , Anthony Lell , Raguram Damodaran
发明人： Ramakrishnan Venkatasubramanian , Anthony Lell , Raguram Damodaran
IPC分类号： H03K21/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A clock divider divides a high speed input clock signal by an odd, even or fractional divide ratio. The clock divider receives a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates a fractional divide ratio when one and an integral divide ratio when zero. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. The clock divider synthesizes one period of an output clock signal in response to each assertion of the count indicator for a fractional divide ratio and synthesizes one period of the output clock signal in response to two assertions of the count indicator for an integral divide ratio.
摘要翻译：时钟分频器将高速输入时钟信号除以奇数，偶数或分数分频比。时钟分频器接收代表分频比N的除法因子值F，其中N可以是奇数或偶数整数。一个分数指示符表示当零和一个积分分频比为零时的分数分频比。当N为偶数时，每N / 2个输入时钟周期，计数指示器被置位。当N为奇数时，计数指示灯交替显示N / 2个输入时钟周期，然后1 + N / 2个输入时钟周期。时钟分频器响应于分数分频比的计数指示器的每个断言而合成输出时钟信号的一个周期，并响应于积分分频比的计数指示符的两个断言来合成输出时钟信号的一个周期。

23. 发明申请

US20120191913A1 Distributed User Controlled Multilevel Block and Global Cache Coherence with Accurate Completion Status 有权
标题翻译：分布式用户控制的多级块和全局缓存一致性与准确的完成状态
公开(公告)号：US20120191913A1
公开(公告)日：2012-07-26
申请号：US13240479
申请日：2011-09-22
申请人： Raguram Damodaran , Abhijeet A. Chachad
发明人： Raguram Damodaran , Abhijeet A. Chachad
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention permits user controlled cache coherence operations with the flexibility to do these operations on all levels of cache together or each level independently. In the case of an all level operation, the user does not have to monitor and sequence each phase of the operation. This invention also provides a way for users to track completion of these operations. This is critical for multi-core/multi-processor devices. Multiple cores may be accessing the end point and the user/application needs to be able to identify when the operation from one core is complete, before permitting other cores access that data or code.
摘要翻译：本发明允许用户控制的高速缓存一致性操作，具有灵活性，可以在所有级别的高速缓存上独立地进行这些操作。在所有级别操作的情况下，用户不必监视和排序操作的每个阶段。本发明还提供了一种用于跟踪这些操作完成的方式。这对于多核/多处理器设备至关重要。在允许其他核心访问该数据或代码之前，多个核心可能正在访问终点，并且用户/应用程序需要能够识别来自一个核心的操作何时完成。

24. 发明申请

US20090172487A1 Multiple pBIST Controllers 有权
标题翻译：多个pBIST控制器
公开(公告)号：US20090172487A1
公开(公告)日：2009-07-02
申请号：US11967148
申请日：2007-12-29
申请人： Raguram Damodaran , Umang Bharatkumar Thakkar , John David Sayre
发明人： Raguram Damodaran , Umang Bharatkumar Thakkar , John David Sayre
IPC分类号： G06F11/27
CPC分类号： G06F11/27
摘要： A system on a single integrated circuit chip (SoC) includes a plurality of operational circuits to be tested. A plurality of programmable built-in self-test (pBIST) controllers is connected to respective ones of the plurality of operational circuits in a manner that allows the pBIST controllers to test the respective operation circuits in parallel. An interface is connected to each of the plurality of pBIST controllers for connection to an external tester to facilitate programming of each of the plurality of pBIST controllers by the external tester, such that the plurality of pBIST controllers are operable to test the plurality of operational circuits in parallel and report the results of the parallel tests to the external tester, thereby reducing test time.
摘要翻译：单个集成电路芯片（SoC）上的系统包括要测试的多个操作电路。多个可编程内置自检（pBIST）控制器以允许pBIST控制器并行测试各个操作电路的方式连接到多个操作电路中的相应的一个操作电路。接口连接到多个pBIST控制器中的每一个，用于连接到外部测试器，以便外部测试器对多个pBIST控制器中的每一个进行编程，使得多个pBIST控制器可操作以测试多个操作电路并行并行测试结果报告给外部测试仪，从而减少测试时间。

25. 发明授权

US07324392B2 ROM-based memory testing 有权
标题翻译：基于ROM的内存测试
公开(公告)号：US07324392B2
公开(公告)日：2008-01-29
申请号：US11422726
申请日：2006-06-07
申请人： Ananthakrishnan Ramamurti , Raguram Damodaran
发明人： Ananthakrishnan Ramamurti , Raguram Damodaran
IPC分类号： G11C7/00 , G11C29/00 , G06F11/00 , G01R31/28
CPC分类号： G11C29/16 , G11C17/14
摘要： This invention uniquely partitions the pBIST ROM for storing program and data information. The pBIST unit selectively loads both the algorithm and data, the algorithm only or the data only for each test set stored in the pBIST ROM into read/write registers. These registers are memory mapped readable/writable. A configuration register has an algorithm bit and a data bit which determines whether the corresponding algorithm or data is loaded from the pBIST ROM. The pBIST unit includes another configuration register having one bit corresponding to each possible test set stored in the pBIST ROM. The pBIST unit runs a test set if the corresponding bit in the configuration register has a first digital state.
摘要翻译：本发明独特地划分用于存储程序和数据信息的pBIST ROM。 pBIST单元选择性地将存储在pBIST ROM中的每个测试集合的算法和数据，仅算法或数据加载到读/写寄存器中。这些寄存器是可读写的内存映射。配置寄存器具有算法位和数据位，用于确定对应的算法或数据是否从pBIST ROM加载。 pBIST单元包括具有与存储在pBIST ROM中的每个可能测试集相对应的一个位的另一个配置寄存器。如果配置寄存器中的相应位具有第一数字状态，则pBIST单元运行测试集。

26. 发明申请

US20070033470A1 Emulation Cache Access for Tag View Reads 有权
标题翻译：标签视图读取的仿真缓存访问
公开(公告)号：US20070033470A1
公开(公告)日：2007-02-08
申请号：US11422740
申请日：2006-06-07
申请人： Raguram Damodaran , Ananthakrishnan Ramamurti
发明人： Raguram Damodaran , Ananthakrishnan Ramamurti
IPC分类号： G01R31/28
CPC分类号： G01R31/3187
摘要： A built-in self test unit reads tag bits of a predetermined cache entry and outputs these tag bits via an external interface. The built-in self test unit enters an emulation mode upon receipt of an emulation signal via the external interface when a first configuration register has a predetermined state. The built-in self test unit then reads tag bits upon each memory mapped read of a second configuration register. The read operation advances to next sequential tag bits upon each memory mapped read of the second configuration register. The tag bits include at least one valid bit and at least one dirty bit. The tag bits also include the most significant bits of the cached address.
摘要翻译：内置自检单元读取预定高速缓存条目的标签位，并通过外部接口输出这些标签位。当第一配置寄存器具有预定状态时，内置自检单元在经由外部接口接收到仿真信号时进入仿真模式。内置的自检单元然后在第二个配置寄存器的每个存储器映射读取时读取标签位。在第二配置寄存器的每次存储器映射读取时，读操作进行到下一个顺序标签位。标签位包括至少一个有效位和至少一个脏位。标记位还包括缓存地址的最高有效位。

27. 发明申请

US20070006033A1 Unique pBIST Features for Advanced Memory Testing 有权
标题翻译：独特的pBIST功能，用于高级内存测试
公开(公告)号：US20070006033A1
公开(公告)日：2007-01-04
申请号：US11422732
申请日：2006-06-07
申请人： Raguram Damodaran , Ananthakrishnan Ramamurti
发明人： Raguram Damodaran , Ananthakrishnan Ramamurti
IPC分类号： G06F11/00
CPC分类号： G06F11/273 , G01R31/3187
摘要： This invention is new built-in self test instructions. A pointer register stores data identifying one bit of a data register. That bit determines whether the data of another data register is used in test in native form or in inverted form. Different built-in self test instructions update pointer including reset to the first bit, no change, increment to the next bit and decrement to the previous bit. For write instructions the selected normal or inverted data is written into memory. For read instructions the selected normal or inverted data is compared with data read from a memory.
摘要翻译：本发明是新的内置自检指令。指针寄存器存储识别数据寄存器的一位的数据。该位确定另一数据寄存器的数据是以本机形式还是以倒置形式用于测试。不同的内置自检指令更新指针，包括复位到第一位，无变化，递增到下一位，并递减到前一位。对于写指令，所选的正常或反相数据被写入存储器。对于读取指令，将所选择的正常或反相数据与从存储器读取的数据进行比较。

28. 发明申请

US20050172180A1 Programmable built in self test of memory 有权
标题翻译：可编程内置自检内存
公开(公告)号：US20050172180A1
公开(公告)日：2005-08-04
申请号：US11003206
申请日：2004-12-03
申请人： Raguram Damodaran , Timothy Anderson , Sanjive Agarwala , Joel Graber
发明人： Raguram Damodaran , Timothy Anderson , Sanjive Agarwala , Joel Graber
IPC分类号： G11C29/00 , G11C29/16
CPC分类号： G11C29/16
摘要： The pBIST solution to memory testing is a balanced hardware-software oriented solution. pBIST hardware provides access to all memories and other such logic (e.g. register files) in pipelined logic allowing back-to-back accesses. The approach then gives the user access to this logic through CPU-like logic in which the programmer can code any algorithm to target any memory testing technique required. Because hardware inside the chip is used at-speed, the full device speed capabilities are available. CPU-like hardware can be programmed and algorithms can be developed and executed after tape-out and while testing on devices in chip form is in process.
摘要翻译：内存测试的pBIST解决方案是一个平衡的面向硬件的软件解决方案。 pBIST硬件提供对允许背靠背访问的流水线逻辑中的所有存储器和其他这样的逻辑（例如寄存器文件）的访问。该方法然后让用户通过类似CPU的逻辑访问该逻辑，其中程序员可以对任何算法进行编码，以定位所需的任何内存测试技术。由于芯片内部的硬件速度被使用，因此可以提供全部设备速度功能。类似CPU的硬件可以进行编程，并且可以在磁带输出之后开发和执行算法，同时在芯片形式的器件上进行测试。

29. 发明申请

US20050132263A1 Memory error detection reporting 有权
标题翻译：内存错误检测报告
公开(公告)号：US20050132263A1
公开(公告)日：2005-06-16
申请号：US10950797
申请日：2004-09-27
申请人： Timothy Anderson , David Bell , Abhijeet Chachad , Peter Dent , Raguram Damodaran
发明人： Timothy Anderson , David Bell , Abhijeet Chachad , Peter Dent , Raguram Damodaran
IPC分类号： G06F11/10 , G11C29/00
CPC分类号： G06F11/1032
摘要： A memory system or a digital signal processor (DSP) includes single-bit-error detection hardware in its level two (L2) memory controller to mitigate the effects of soft errors. Error detection hardware detects erroneous data that is fetched by the central processing unit and signals the central processing unit. The parity is generated and checked only for whole memory line accesses. This technique is especially useful for cache memory. The central processing unit can query the memory controller as to the specific location that generated the error and decide the next course of action based on the type of data affected.
摘要翻译：存储器系统或数字信号处理器（DSP）包括其二级（L2）存储器控制器中的单位错误检测硬件，以减轻软错误的影响。错误检测硬件检测由中央处理单元取出并向中央处理单元发出信号的错误数据。仅对整个存储器线路访问生成和检查奇偶校验。这种技术对缓存特别有用。中央处理单元可以根据生成错误的特定位置查询存储器控制器，并根据受影响的数据类型决定下一个操作过程。

30. 发明授权

US09195610B2 Transaction info bypass for nodes coupled to an interconnect fabric 有权
标题翻译：交换信息绕过耦合到互连结构的节点
公开(公告)号：US09195610B2
公开(公告)日：2015-11-24
申请号：US13241175
申请日：2011-09-22
申请人： Dheera Balasubramanian , Raguram Damodaran
发明人： Dheera Balasubramanian , Raguram Damodaran
IPC分类号： G06F12/12 , G06F7/483 , G06F9/30 , G06F11/10 , G06F13/16 , G06F13/18 , G06F1/32 , G06F12/02 , G06F13/364 , H03M13/35 , H03M13/29 , H03K19/00 , H03K21/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A shared resource within a module may be accessed by a request from an external requester. An external transaction request may be received from an external requester outside the module for access to the shared resource that includes control information, not all of which is needed to access the shared resource. The external transaction request may be modified to form a modified request by removing a portion of the locally unneeded control information and storing the unneeded portion of control information as an entry in a bypass buffer. A reply received from the shared resource may be modified by appending the stored portion of control information from the entry in the bypass buffer before sending the modified reply to the external requester.
摘要翻译：模块内的共享资源可以通过来自外部请求者的请求来访问。可以从模块外部的外部请求者接收外部事务请求，以访问包括控制信息的共享资源，而不是所有这些都需要访问共享资源。外部事务请求可以被修改以通过去除局部不需要的控制信息的一部分并且将不需要的控制信息部分作为条目存储在旁路缓冲器中来形成修改的请求。从共享资源接收到的答复可以通过在向外部请求者发送修改的回复之前，从旁路缓冲器中的条目附加控制信息的存储部分来修改。

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