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21. 发明授权

US09263581B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09263581B2
公开(公告)日：2016-02-16
申请号：US14394802
申请日：2012-05-30
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
IPC分类号： H01L23/62 , H01L29/78 , H01L29/66 , H01L29/786 , H01L21/265 , H01L21/324 , H01L29/06
CPC分类号： H01L29/7849 , H01L21/265 , H01L21/26506 , H01L21/2652 , H01L21/324 , H01L29/0649 , H01L29/66545 , H01L29/66583 , H01L29/66772 , H01L29/78654
摘要： A method for manufacturing a semiconductor structure comprises the following steps: providing an SOI substrate and forming a gate structure on the SOI substrate; implanting ions to induce stress in the semiconductor structure by using the gate structure as mask to form a stress-inducing region, which is located under the BOX layer on the SOI substrate on both sides of the gate structure. A semiconductor structure manufactured according to the above method is also disclosed. The semiconductor structure and the method for manufacturing the same disclosed in the present application form on the ground layer a stress-inducing region, which provides favorable stress to the semiconductor device channel and contributes to the improvement of the semiconductor device performance.
摘要翻译：一种制造半导体结构的方法包括以下步骤：在SOI衬底上提供SOI衬底并形成栅极结构; 通过使用栅极结构作为掩模来注入离子以在半导体结构中引起应力，以形成位于栅极结构两侧的SOI衬底上的BOX层下方的应力诱导区域。还公开了根据上述方法制造的半导体结构。在本申请中公开的半导体结构及其制造方法在地层上形成应力诱导区域，其对半导体器件沟道提供有利的应力，有助于提高半导体器件的性能。

22. 发明授权

US09178070B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09178070B2
公开(公告)日：2015-11-03
申请号：US13138053
申请日：2011-03-04
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/12 , H01L29/786 , H01L29/423 , H01L29/66
CPC分类号： H01L29/78648 , H01L29/42384 , H01L29/66772 , H01L29/78603
摘要： The present application discloses a semiconductor structure and a method for manufacturing the same. A semiconductor structure according to the present invention can adjust the threshold voltage by capacitive coupling between a backgate region either and a source region or a drain region with a common contact, i.e. a source contact or a drain contact, which leads to a simple manufacturing process, a higher integration level, and a lower manufacture cost. Moreover, the asymmetric design of the backgate structure, together with the doping of the backgate region which can be varied as required in an actual device design, can further enhance the effects of adjusting the threshold voltage and improve the performances of the device.
摘要翻译：本申请公开了一种半导体结构及其制造方法。根据本发明的半导体结构可以通过在具有公共接触的源极区域或漏极区域之间的电容耦合来调节阈值电压，即源极接触或漏极接触，这导致简单的制造过程，更高的集成度，更低的制造成本。此外，背栅结构的非对称设计以及可以根据实际器件设计中所需而改变的背栅区域的掺杂，可以进一步增强调节阈值电压并提高器件性能的效果。

23. 发明授权

US08766371B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08766371B2
公开(公告)日：2014-07-01
申请号：US13256866
申请日：2011-02-25
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/70
CPC分类号： H01L29/4983 , H01L21/823807 , H01L21/823842 , H01L21/823864 , H01L29/66545 , H01L29/7845
摘要： There is provided a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention comprises: a semiconductor substrate; a channel region formed on the semiconductor substrate; a gate stack formed on the channel region; and source/drain regions formed on both sides of the channel region and embedded in the semiconductor substrate. The gate stack comprises: a gate dielectric layer formed on the channel region; and a conductive layer positioned on the gate dielectric layer. For an nMOSFET, the conductive layer has a compressive stress to apply a tensile stress to the channel region; and for a pMOSFET, the conductive layer has a tensile stress to apply a compressive stress to the channel region.
摘要翻译：提供半导体结构及其制造方法。根据本发明的半导体结构包括：半导体衬底; 形成在半导体衬底上的沟道区; 形成在沟道区上的栅叠层; 以及形成在沟道区两侧并嵌入在半导体衬底中的源/漏区。栅极堆叠包括：形成在沟道区上的栅极电介质层; 以及位于栅介质层上的导电层。对于nMOSFET，导电层具有将压应力施加到沟道区的压应力; 并且对于pMOSFET，导电层具有拉伸应力以向沟道区域施加压应力。

24. 发明申请

US20130009244A1 MOSFET AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US20130009244A1
公开(公告)日：2013-01-10
申请号：US13379444
申请日：2011-08-01
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/2652 , H01L21/2658 , H01L29/42384 , H01L29/78648
摘要： The present application discloses an MOSFET and a method for manufacturing the same. The MOSFET comprises: a semiconductor substrate; a first insulation buried layer disposed on the semiconductor substrate; a back gate formed in a first semiconductor layer which is disposed on the first insulation buried layer; a second insulation buried layer disposed on the first semiconductor layer; source/drain regions formed in a second semiconductor layer which is disposed on the second insulation buried layer; a gate disposed on the second semiconductor layer; and electric connections to the source/drain regions, the gate and the back gate, wherein the back gate comprises first back gate regions of a first conductivity type which are disposed under the source/drain regions and a second back gate region of a second conductivity type which is disposed under a channel region, the first back gate regions adjoins the second back gate region, the first conductivity type is opposite to the second conductivity type, and the electric connection to the back gate comprise a conductive via contacted with one of the first back gate regions. The MOSFET, of any conductivity type, can have adjustable threshold voltage and reduced leakage current via the back gate between the source/drain regions by using the back gate in the form of a PNP junction or an NPN junction.
摘要翻译：本申请公开了一种MOSFET及其制造方法。 MOSFET包括：半导体衬底; 设置在所述半导体基板上的第一绝缘埋层; 形成在第一绝缘掩埋层上的第一半导体层中形成的背栅; 设置在所述第一半导体层上的第二绝缘埋层; 源极/漏极区域，形成在第二绝缘掩埋层上的第二半导体层中; 设置在所述第二半导体层上的栅极; 以及与源极/漏极区域，栅极和背栅极的电连接，其中所述背栅极包括设置在所述源极/漏极区域下方的第一导电类型的第一后栅极区域和具有第二导电性的第二背栅极区域所述第一导电类型与所述第二导电类型相反，并且与所述第二导电类型的电连接包括与所述第二导电类型之一接触的导电通孔，第一个后门区域。任何导电类型的MOSFET可以通过使用PNP结或NPN结形式的背栅，通过源极/漏极区之间的背栅极具有可调节的阈值电压和减小的漏电流。

25. 发明申请

US20120326155A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120326155A1
公开(公告)日：2012-12-27
申请号：US13376247
申请日：2011-08-02
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/84 , H01L21/823828 , H01L21/823878 , H01L27/1203 , H01L29/4908 , H01L29/78603 , H01L29/78612
摘要： The present application discloses a semiconductor structure and method for manufacturing the same. The semiconductor structure comprises: an SOI substrate and a MOSFET formed on the SOI substrate, wherein the SOI substrate comprises, in a top-down fashion, an SOI layer, a first buried insulator layer, a buried semiconductor layer, a second buried insulator layer, and a semiconductor substrate, the buried semiconductor layer including a backgate region including a portion of the buried semiconductor layer doped with a dopant of a first polarity; the MOSFET comprises a gate stack and source/drain regions, the gate stack being formed on the SOI layer, and the source/drain regions being formed in the SOI layer at opposite sides of the gate stack; and the backgate region includes a counter-doped region, the counter-doped region is self-aligned with the gate stack and includes a dopant of a second polarity, and the second polarity is opposite to the first polarity. The embodiment of the present disclosure can be used for adjusting a threshold voltage of a MOSFET.
摘要翻译：本申请公开了一种半导体结构及其制造方法。半导体结构包括：SOI衬底和形成在SOI衬底上的MOSFET，其中SOI衬底以自顶向下的方式包括SOI层，第一掩埋绝缘体层，埋入半导体层，第二掩埋绝缘体层和半导体衬底，所述掩埋半导体层包括背栅区，所述背栅区包括掺杂有第一极性的掺杂剂的所述掩埋半导体层的一部分; MOSFET包括栅极堆叠和源极/漏极区，栅极堆叠形成在SOI层上，并且源极/漏极区域形成在栅极堆叠的相对侧的SOI层中; 并且所述背栅区域包括反掺杂区域，所述反掺杂区域与所述栅叠层自对准并且包括第二极性的掺杂剂，并且所述第二极性与所述第一极性相反。本公开的实施例可以用于调整MOSFET的阈值电压。

26. 发明授权

US07897468B1 Device having self-aligned double gate formed by backside engineering, and device having super-steep retrograded island 有权
标题翻译：具有通过背面工程形成的自对准双门的装置，以及具有超陡峭退化岛的装置
公开(公告)号：US07897468B1
公开(公告)日：2011-03-01
申请号：US12556604
申请日：2009-09-10
申请人： Zhijiong Luo , Qingqing Liang , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Qingqing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L29/1083 , H01L29/165 , H01L29/66484 , H01L29/6659 , H01L29/66636 , H01L29/66742 , H01L29/7831 , H01L29/78648
摘要： A method of forming a dual gate semiconductor device is provided that includes providing a substrate having a first semiconductor layer and a second semiconductor layer, in which a first gate structure is formed on the second semiconductor layer. The second semiconductor layer and the first semiconductor layer are etched to expose the substrate using the first gate structure as an etch mask. A remaining portion of the first semiconductor layer is present underlying the first gate structure having edges aligned to the edges of the first gate structure. An epitaxial semiconductor material is formed on exposed portions of the substrate. The substrate and the remaining portion of the first semiconductor layer are removed to provide a recess having edges aligned to the edges of the first gate structure, and a second gate structure is formed in the recess. A method of forming a retrograded island is also provided.
摘要翻译：提供一种形成双栅极半导体器件的方法，其包括提供具有第一半导体层和第二半导体层的衬底，其中在第二半导体层上形成第一栅极结构。蚀刻第二半导体层和第一半导体层以使用第一栅极结构作为蚀刻掩模来露出衬底。第一半导体层的剩余部分位于具有与第一栅极结构的边缘对准的边缘的第一栅极结构下方。在衬底的暴露部分上形成外延半导体材料。去除衬底和第一半导体层的剩余部分以提供具有与第一栅极结构的边缘对准的边缘的凹部，并且在凹部中形成第二栅极结构。还提供了形成退火岛的方法。

27. 发明授权

US10096717B2 MOSFET and method for manufacturing the same 有权
公开(公告)号：US10096717B2
公开(公告)日：2018-10-09
申请号：US13510407
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/336 , H01L29/786 , H01L21/265 , H01L29/66 , H01L21/74
摘要： The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; and a channel region in the semiconductor layer and located between the source region and the drain region, wherein the MOSFET further comprises a back gate which is located in the semiconductor substrate and has a first doped region as a lower portion of the back gate and a second doped region as an upper portion of the back gate, and the second doped region of the back gate is self-aligned with the gate stack. The MOSFET can adjust a threshold voltage by changing doping type and doping concentration of the back gate.

28. 发明授权

US09583622B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09583622B2
公开(公告)日：2017-02-28
申请号：US14407263
申请日：2012-07-06
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin , Qingqing Liang
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin , Qingqing Liang
IPC分类号： H01L27/12 , H01L29/78 , H01L29/66 , H01L29/732 , H01L29/737 , H01L29/786 , H01L21/02 , H01L21/265 , H01L21/306 , H01L21/324 , H01L21/762 , H01L29/04 , H01L29/06 , H01L29/16 , H01L29/161
CPC分类号： H01L29/7849 , H01L21/0245 , H01L21/02513 , H01L21/265 , H01L21/30604 , H01L21/324 , H01L21/76224 , H01L21/76254 , H01L21/76283 , H01L29/04 , H01L29/0653 , H01L29/16 , H01L29/161 , H01L29/66242 , H01L29/66272 , H01L29/66568 , H01L29/66772 , H01L29/732 , H01L29/7371 , H01L29/78654
摘要： The present invention discloses a semiconductor structure and a method for manufacturing the same, which comprises providing a substrate, and forming a stress layer, a buried oxide layer, and an SOI layer on the substrate; forming a doped region of the stress layer arranged in a specific position in the stress layer; forming an oxide layer and a nitride layer on the SOI layer, and forming a first trench that etches the nitride layer, the oxide layer, the SOI layer, and the buried oxide layer, and stops on the upper surface of the stress layer, and exposes at least part of the doped region of the stress layer; forming a cavity by wet etching through the first trench to remove the doped region of the stress layer; forming a polycrystalline silicon region of the stress layer and a second trench by filling the cavity with polycrystalline silicon and etching back; forming an isolation region by filling the second trench. The semiconductor structure and the method for manufacturing the same disclosed in the present invention provide a favorable stress for the channel of the semiconductor device by introducing a stress layer and a stress induced zone set at specific positions depending on device type to help improving the performance of the semiconductor device.
摘要翻译：本发明公开了一种半导体结构及其制造方法，其特征在于，在基板上设置基板，形成应力层，埋入氧化物层，SOI层，在应力层中形成布置在特定位置的应力层的掺杂区域; 在所述SOI层上形成氧化物层和氮化物层，形成蚀刻所述氮化物层，所述氧化物层，所述SOI层和所述埋入氧化物层的第一沟槽，并停止在所述应力层的上表面上，以及暴露应力层的掺杂区域的至少一部分; 通过所述第一沟槽的湿蚀刻形成空腔以移除所述应力层的掺杂区域; 通过用多晶硅填充空腔并回蚀而形成应力层的多晶硅区域和第二沟槽; 通过填充第二沟槽形成隔离区域。在本发明中公开的半导体结构及其制造方法通过根据器件类型在特定位置引入应力层和应力诱导区域来为半导体器件的沟道提供有利的应力，以有助于提高半导体器件。

29. 发明授权

US09087691B2 Method for manufacturing graphene nano-ribbon, mosfet and method for manufacturing the same 有权
标题翻译：石墨烯纳米带的制造方法，其制造方法及其制造方法
公开(公告)号：US09087691B2
公开(公告)日：2015-07-21
申请号：US13510390
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/20 , H01L21/36 , H01L21/02 , H01L29/775 , H01L29/06 , H01L29/16 , H01L29/20 , H01L29/66 , H01L29/786 , B82Y10/00 , B82Y40/00 , B82Y30/00
CPC分类号： H01L21/0242 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/02422 , H01L21/02488 , H01L21/02491 , H01L21/02507 , H01L21/02527 , H01L21/02639 , H01L29/0673 , H01L29/1606 , H01L29/2003 , H01L29/66742 , H01L29/775 , H01L29/78684 , H01L29/78696
摘要： A MOSFET with a graphene nano-ribbon, and a method for manufacturing the same are provided. The MOSFET comprises an insulating substrate; and an oxide protection layer on the insulating substrate. At least one graphene nano-ribbon is embedded in the oxide protection layer and has a surface which is exposed at a side surface of the oxide protection layer. A channel region is provided in each of the at least one graphene nano-ribbon. A source region and a drain regions are provided in each of the at least one graphene nano-ribbon. The channel region is located between the source region and the drain region. A gate dielectric is positioned on the at least one graphene nano-ribbon. A gate conductor on the gate dielectric. A source and drain contacts contact the source region and the drain region respectively on the side surface of the oxide protection layer.
摘要翻译：提供了具有石墨烯纳米带的MOSFET及其制造方法。 MOSFET包括绝缘基板; 和绝缘基板上的氧化物保护层。至少一个石墨烯纳米带被嵌入在氧化物保护层中并且具有暴露在氧化物保护层的侧表面的表面。在所述至少一个石墨烯纳米带的每个中设置有沟道区。在所述至少一个石墨烯纳米带的每一个中设置源极区和漏极区。沟道区位于源区和漏区之间。栅电介质位于至少一个石墨烯纳米带上。栅极电介质上的栅极导体。源极和漏极触点分别在氧化物保护层的侧表面上接触源极区域和漏极区域。

30. 发明授权

US09018739B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09018739B2
公开(公告)日：2015-04-28
申请号：US13060468
申请日：2010-09-25
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L29/04 , H01L29/78 , H01L29/10 , H01L29/165 , H01L29/49 , H01L29/51 , H01L29/66
CPC分类号： H01L29/7834 , H01L29/045 , H01L29/105 , H01L29/1054 , H01L29/1083 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/66651
摘要： The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate; a first semiconductor layer on the semiconductor substrate; a second semiconductor layer surrounding the first semiconductor layer; a high k dielectric layer and a gate conductor formed on the first semiconductor layer; source/drain regions formed in the second semiconductor layer, wherein the second semiconductor layer has a slant sidewall in contact with the first semiconductor layer. The semiconductor device has an increased output current, an increased operating speed, and a reduced power consumption due to the channel region of high mobility.
摘要翻译：本申请公开了一种半导体器件及其制造方法。半导体器件包括半导体衬底; 半导体衬底上的第一半导体层; 围绕所述第一半导体层的第二半导体层; 形成在第一半导体层上的高k电介质层和栅极导体; 形成在第二半导体层中的源/漏区，其中第二半导体层具有与第一半导体层接触的倾斜侧壁。半导体器件具有增加的输出电流，增加的操作速度以及由于高移动性的沟道区域而导致的功率消耗降低。

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